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| revision history as4c128m32md2 - 134 ball fbga package revision details date rev 1.0 preliminary datasheet jun 201 6 alliance memory inc. 511 taylor way, san carlos, ca 94070 tel: (650) 610-6800 fax: (650) 620-9211 alliance memory inc. reserves the right to change products or specification without notice AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -1?103- rev.1.0 june 2016
specifications - density : 4g bits - organization : - 16m words x 32 bits x 8 banks - package : - 134-ball fbga - lead-free (rohs compliant) and halogen-free - power supply : - vdd1 = 1.8v (1.7v~1.95v) - vdd2/vddq/vddca = 1.2v (1.14v~1.3v) - hsul_12 interface (high speed unterminated logic 1.2v) - data rate : - 1066mbps rl=8 - burst lengths (bl) : 4, 8 and 16 - burst type (bt) : sequential and interleave - read latency (rl) : 3, 4, 5, 6, 7, 8 - write latency (wl) : 1, 2, 3, 4 - output driver impedanc e: 34.3/40/48/60/80/120 - operating case temperature range - commercial tc = -25c to +85c - industrial tc = -40c to +85c features - jedec lpddr2-s4b compliance - low power consumption - four-bit prefetch ddr architecture - eight internal banks for concurrent operation - double data rate architecture for command, address and data bus - bidirectional and differential data strobe per byte of data (dqs and dqs ) - dqs is edge-aligned with data for reads, center- aligned with data for writes - differential clock inputs (ck and ck ) - data mask (dm) for write data - programmable read and write latencies (rl/wl) - auto refresh and self refresh - per-bank refresh for concurrent operation - partial-array self refresh (pasr) - on-chip temperature sensor to control self refresh rate for temperature compensated self refresh (tcsr) - deep power-down mode (dpd) - selectable output drive strength (ds) - clock stop capability - dq calibration offering specific dq output patterns - zq calibration table 1. ordering information part number org temperature maxclock (mhz) package AS4C128M32MD2-18BCN 128 mx32 commercial -25c to + 85c 533 134-ball fbga table 2. speed grade information speed grade clock frequency rl trcd (ns) trp (ns) ddr2l-1066 533mhz 8 18 18 as4c128m32md2-18bin 128 mx32 industrial -40c to +85c 533 134-ball fbga AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -2?103- rev.1.0 june 2016 pin configurations - 11.5mmx11.5mm 134b fbga signal pin description pin type function ck, ck (ck, ck#) (ck_t, ck_c) input clock : ck and ck are differential clock inputs. all ca inputs are sampled onboth rising and falling edges of ck. cs and cke inputs are sampled at the risingedge of ck. ac timings are referenced to clock. cke input clock enable : cke high activates and cke low deactivates the internal clocksignals, input buffers, and output drivers. power-saving modes are entered andexited via cke transitions. cke is considered part of the command code. cke issampled at the rising edge of ck. cs (cs#) (cs_n) input chip select : cs is considered part of the command code and is sampled at therising edge of ck. ca0~ca9 input command/address inputs: provide the command and address inputs accordingto the command truth table. dm0~dm3 input input data mask : dm is an input mask signal for write data. although dm ballsare input-only, the dm loading is designed to match that of dq and dqs balls. dm[3:0] is dm for each of the four data bytes, respectively. dq0~dq31 input/output data input/output: bidirectional data bus. dqs[3:0] (dqs_t[3:0]), dqs [3:0] dqs#[3:0] (dqs_c[3:0]) input/output data strobe: the data strobe is bidirectional (used for read and write data) andcomplementary (dqs and dqs ). it is edge-aligned output with read data and centered input with write data. dqs[3:0]/ dqs [3:0] is dqs for each of the four data bytes, respectively. nc no connect: no internal electrical connection is present. zq input external impedance (240 ohm): this signal is used to cali brate the device out-put impedance. vdd1 supply core power: supply 1. vdd2 supply core power: supply 2. vddq supply dq power supply: isolated on the die for improved noise immunity. vddca supply command/address power supply: command/address power supply. vrefdq, vrefca supply reference voltage: vrefca is reference for command/address input buffers,vrefdq is reference for dq input buffers. vss supply common ground AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -4?103- rev.1.0 june 2016 functional block diagram 128mb x 32 lpddr2 v refca & 6 cke ck & . dm [3:0] ca [9:0] v refdq zq rzq dq [31:0] dqs [3:0] lpddr2 die 0 v ss v dd1 v dd2 v ddq v ddca AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -5?103- rev.1.0 june 2016 simplified state diagram AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -6?103- rev.1.0 june 2016 basic functionality lpddr2-s4 uses the double data rate architecture on the command/address (ca) bus to reduce the number of input pins in the system. the 10-bit ca bus contains command , address, and bank/row buff er information. each command uses one clock cycle, during which comm and information is transferred on both the positive and neg ative edge of the clock. prior to normal operation, the ddr3 sdram must be powered up and initialized in a predefined manner. the fol- lowing sections provide detailed information covering device reset and initialization, register definition, command descriptions and device operation. to achieve high-speed operation, our lpddr2-s4 sdram uses the double data rate architecture and adopt 4n- prefetch interface desig ned to transfer two data per clock cycle at th e i/o pins. a single read or write access for the lpddr2-s4 effectively consists of a single 4n-bit wide, on e clock cycle data transfer at the internal sdram core and four corresponding n-bit wide, one-half-clock-cycle data tr ansfer at the i/o pins. read and write accesses to the lpddr2-s4 are burst oriented; accesses start at a selected location and continue for a programmed number of loca- tions in a programmed sequence. for lpddr2-s4 devices, accesses begin with the registration of an active command, which is then followed by a read or write command. the address and ba bits registered coinci dent with the active command are used to select the row and the bank to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. an auto precharge function may be enabled to provide a self-timed row precharge that is initia ted at the end of the burst access. as with standard ddr sdrams, the pipelined, multib ank architecture of the lpddr2-s4 sdrams supports concurrent operation, thereby providin g high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power saving power-down mode. deep power-down mode is offered to achieve maximum power reduction by elimin ating the power of the memory array. data will not be retained after device enters deep power-down mode. two self refresh features, te mperature-compensated self refresh (tcsr) and partial array self refresh (pasr), offer additional power saving. tc sr is controlled by the automatic on-chip temperature sen- sor. the pasr can be customized using the extended mode register settings. the two features may be combined to achieve even greater power saving. the dll that is typically used on standar d ddr devices is not necessary on the lpddr2-s4 sdram. it has been omitted to save power. prior to normal operation, the lpddr2-s4 sdram must be in itialized. the following sections provide detailed informa- tion covering device initialization, register def inition, command descriptions and device operation. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -7?103- rev.1.0 june 2016 power-up, initialization, and power-off lpddr2 devices must be powered up and initialized in a pre defined manner. power-up and initialization by means other than those specified will result in undefined operation. power ramp and device initialization the following sequence must be used to power up the device . unless specified otherwise, this procedure is mandatory and applies to devices. voltage ramp: while applying power (after ta), cke must be held low (=<0.2 x vddca), and all other inputs must be between vilmin and vihmax. the device outputs remain at high-z while cke is held low. following the completion of the voltage ramp (tb), cke must be maintained low. dq, dm, dqs and dqs voltage levels must be between vssq and vddq during voltage ramp to avoid latch up. ck, ck , cs , and ca input levels must be between vssca and vddca during voltage ramp to avoid latch-up. the following conditions apply: ta is the point where any power supply first reaches 300 mv. after ta is reached, vdd1 must be greater than vdd2 - 200 mv. after ta is reached, vdd1 and vdd2 must be greater than vddca - 200 mv. after ta is reached, vdd1 and vdd2 must be greater than vddq - 200 mv. after ta is reached, vref must always be less than all other supply voltages. the voltage difference between any of vss, vssq, and vssca pins may not exceed 100 mv. tb is the point when all supply voltages are within their respective min/max operating conditions. reference voltages shall be within their respec tive min/max operating conditions a mini mum of 5 clocks before cke goes high. power ramp duration tinit0 (tb - ta) must be no greater than 20 ms. for supply and reference voltage operating conditions, see dc power table. beginning at tb, cke must remain low for at least tinit1 = 100 ns, after which cke can be asserted high. the clock must be stable at least tinit2 = 5 x tck prior to the first cke low-to-high transition (tc). cke, cs , and ca inputs must observe setup and hold requirements (tis, tih) with respect to the first rising clock edge (as well as to subsequent falling and rising edges). if any mrrs are issued, the clock period must be within the range defined for tckb (18ns to 100ns). mrws can be issued at normal clock frequencies as long as all ac timing s are met. some ac parameters (for example, tdqsck) could have relaxed timings (such as tdqsckb) before the system is appropriately configured. while keeping cke high, nop commands must be issued for at least tinit3 = 200us (td). reset command: after tinit3 is satisfied, the mrw reset command must be issued (td). an optional precharge all command can be issued prior to the mrw reset command. wait at leas t tinit4=1us while keeping cke asserted and issuing nop commands. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -8?103- rev.1.0 june 2016 mrrs and device auto initialization (dai) polling: after tinit4 is satisfied (te), only mrr commands and power-down entry/exit commands ar e supported. after te, cke can go low in alignment with power-down entry and exit spec ifications. use the mrr command to poll the dai bit and report when device auto initialization is complete; otherwise, the contro ller must wait a minimum of tinit5, or until the dai bit is set before proceeding. as the memory output buffers are not properly configured by te, some ac parameters must have relaxed timings before the system is appropriately configured. after the dai bi t (mr0, dai) is set to zero by the memory device (dai complete), the device is in the idle state (tf ). dai status can be determined by issuing the mrr command to mr0. the device sets the dai bit no later than ti nit5 after the reset command. the controller must wait at least tinit5 or until the dai bit is set before proceeding. zq calibration: after tinit5 (tf ), the mrw initialization calibration (z q_cal) command can be issued to the memory (mr10). for lpddr2 devices that do not support zq calibration, this co mmand will be ignored. this command is used to calibrate output impedance over process, voltage, and temperat ure. in systems where more than one lpddr2 device exists on the same bus, the controller must not overlap mrw zq_cal commands. the device is ready for normal operation after tzqinit. normal operation: after tzqinit (tg), mrw commands must be used to properly configure the memory (for exam ple the output buffer drive strength, latencies, etc.). specifically, mr1, mr2, and mr3 must be set to configure the memory for the target frequency and memory configuration.after the initialization sequence is complete, the device is ready for any valid command. after tg, the clock frequency can be changed using the proc edure described in ?input clock frequency changes and clock stop events?. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -9?103- rev.1.0 june 2016 power ramp and initiali zation sequence s ymbol va lue unit comment min m a x t init0 2 0msm aximum power ra mp time t init1 100 ns minimum cke low time a fter completion of power r a mp t init 2 5 tck minimum st a ble clock before first cke high t init3 2 00 p s minimum idle time a fter first cke a ssertion t init4 1 p s minimum idle time a fter reset comm and t init5 s : 10 p s m a ximum dura tion of device a uto-initi a liza tion n: vendor p s t z q init 1 p s z q initi a l ca libr a tion for lpddr 2 - s 4 a nd lpddr 2 -n devices t ck e 18 100 ns clock cycle time during boot ck_t / ck_c s upplies cke c a * d q t iscke t init0 = 20 ms (max) t init3 = 200 us (min) t init1 = 100 ns (min) t init2 = 5 t ck (min) t init4 = 1 us (min) t init5 * midlevel on c a bus me a ns: va lid nop pd res et mrr z q c ta tb tc td te tf vali d t zqinit tg AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -10 ? 103- rev.1.0 june 2016 initialization after reset (without voltage ramp) if the reset command is issued before or after the power -up initialization sequence, the re-initialization procedure must begin at td. power-off sequence use the following sequence to power off the device. unless specified otherwise, this procedure is mandatory and applies to devices. while powering off, cke must be held lo w (=< 0.2 x vddca); all other inputs must be between vilmin and vihmax. the device outputs remain at high-z while cke is held low. dq, dm, dqs, and dqs voltage levels must be between vssq and vddq during the power-off sequence to avoid latch-up. ck, ck , cs , and ca input levels must be between vssca and vddca during the power-off sequence to avoid latch-up. tx is the point where any power supply decreases under its minimum value specified in the dc operating condition table. tz is the point where all power supplies are below 300 mv. after tz, the device is powered off. the time between tx and tz (tpoff) shall be less than 2s. the following conditions apply: between tx and tz, vdd1 must be greater than vdd2 - 200 mv. between tx and tz, vdd1 and vdd2 must be greater than vddca - 200 mv. between tx and tz, vdd1 and vdd2 mu st be greater than vddq - 200 mv. between tx and tz, vref must always be less than all other supply voltages. the voltage difference between any of vss, vssq, and vssca pins may not exceed 100 mv. uncontrolled power-off sequence when an uncontrolled power-off occurs, the following conditions must be met: at tx, when the power supply drops below the minimum values specified, all power supplies must be turned off and all power-supply current capacity mu st be at zero, except for any static charge remaining in the system . after tz (the point at which all power supplies first reach 300mv), the device must power off. the time between tx and tz must not exceed 2s. during this period, the relative voltage between power su pplies is uncontrolled. vdd1 and vdd2 must decrease with a slope lower than 0.5 v/us between tx and tz. an uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device. symbol value unit comment min max tpoff - 2 s maximum power-off ramp time AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -11 ? 103- rev.1.0 june 2016 mode register definition lpddr2 devices contain a set of mode registers used for programming device operating parameters, reading device information and status, and for initiating special operations such as dq calibration, zq calibration, and device reset. mode register assignment and definition table below shows the mode registers for lpddr2 sdram. each register is denoted as ?r?, if it can be read but not written, ?w? if it can be written but not read, and ?r/w? if it can be read and wr itten. mode register read command shall be used to read a register. mode register writ e command shall be used to write a register. mode register assignment mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 00 00 h device info. r (rfu) da dai 01 01 h device feature1 w nwr (for ap) wc bt bl 02 02 h device feature2 w (rfu) rl & wl 03 03 h i/o config-1 w (rfu) ds 04 04 h refresh rate r tuf (rfu) refresh rate 05 05 h basic config-1 r lpddr2 manufacturer id 06 06 h basic config-2 r revision id1 07 07 h basic config-3 r revision id2 08 08 h basic config-4 r i/o width density type 09 09 h test mode w vendor-specific test mode 10 0a h io calibration w calibration code 11~15 0b h ~0f h (reserved) (rfu) 16 10 h pasr_bank w bank mask 17 11 h pasr_seg w segment mask 18~19 12 h ~13 h (reserved) (rfu) 20~31 18 h ~1f h reserved for nvm 32 20 h dq calibration pattern a r see ?data calibration pattern description? 33~39 21 h ~27 h (do not use) 40 28 h dq calibration pattern b r see ?data calibration pattern description? 41~47 29 h ~2f h (do not use) 48~62 30 h ~3e h (reserved) (rfu) 63 3f h reset w x 64~126 40 h ~7e h (reserved) (rfu) 127 7f h (do not use) 128~190 80 h ~be h (reserved) (rfu) AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -12 ? 103- rev.1.0 june 2016 notes: 1. rfu bits shall be set to ?0 ? during mode register writes. 2. rfu bits shall be read as ?0? during mode register reads. 3. all mode registers from that are specified as rfu or write-only shall retu rn undefined data when read and dqs shall be toggled. 4. all mode registers that are specif ied as rfu shall not be written. 5. writes to read-only registers shall have no impact on the functionality of the device. mr0_device information (ma<7:0> = 00h) mr1_device feature 1 (ma<7:0> = 01h) 191 bf h (do not use) 192~254 c0 h ~fe h (reserved) (rfu) 255 ff h (do not use) mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 00 00 h device info. r (rfu) da dai op0 di (device information) read-only 0b: dai complete 1b: dai still in progress op1 dai (device auto-initialization st atus) read-only 0b: s2 or s4 sdram 1b: do not use mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 01 01 h device feature1 w nwr (for ap) wc bt bl op<2:0> bl (burst length) write-only 010b: bl4 (default) 011b: bl8 100b: bl16 all others: reserved op3 bt*1 (burst type) write-only 0b: sequential (default) 1b: interleaved (allowed for sdram only) op4 wc (wrap) write-only 0b: wrap (default) 1b: no wrap (allowed for sdram bl4 only) op<7:5> nwr*2 write-only 001b: nwr=3 (default) 010b: nwr=4 011b: nwr=5 100b: nwr=6 101b: nwr=7 110b: nwr=8 all others: reserved mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -13?103- rev.1.0 june 2016 notes: 1. bl16, interleaved is not an offi cial combination to be supported. 2. programmed value in nwr register is the number of clock cycles which determ ines when to start internal precharge operation for a write burst with ap enabled. it is determined by ru(twr/tck). burst sequence by bl, bt, and wc notes: 1. c0 input is not present on ca bus. it is implied zero. 2. for bl=4, the burst address represents c1 - c0. 3. for bl=8, the burst address represents c2 - c0. 4. for bl=16, the burst address represents c3 - c0. 5. for no-wrap, bl4, the burst must not cross the page boundary or the sub-p age boundary. the variable y can start at any address with c0 equal to 0, but must not start at any address shown bellow. c 3 c2 c1 c0 wc bt bl burst cycle number and bur st address sequence 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 x x 0 b 0 b wra p a ny 4 012 3 x x 1 b 0 b 2 301 x xx 0 b nw a ny y y+1 y+2 y+3 x 0 b 0 b 0 b wra p seq 8 012 345 6 7 x 0 b 1 b 0 b 2 345 6 701 x 1 b 0 b 0 b 456 701 2 3 x 1 b 1 b 0 b 6 701 2 345 x 0 b 0 b 0 b int 012 345 6 7 x 0 b 1 b 0 b 2 301 6 745 x 1 b 0 b 0 b 456 701 2 3 x 1 b 1 b 0 b 6 745 2 301 xxx 0 b nw a ny illegal (not allowed) 0 b 0 b 0 b 0 b wra p seq 1 6 012 345 6 78 9 a bcdef 0 b 0 b 1 b 0 b 2 345 6 789 a bcdef 0 1 0 b 1 b 0 b 0 b 456 789 a bc d e f 0 1 2 3 0 b 1 b 1 b 0 b 6 789 a bcde f 0 1 2 345 1 b 0 b 0 b 0 b 89 a bcdef01 2 345 6 7 1 b 0 b 1 b 0 b a bcdef01 2 345 6 789 1 b 1 b 0 b 0 b cdef01 2 34 5 6 789 a b 1 b 1 b 1 b 0 b ef01 2 345 6 789 a bcd xxx 0 b int illegal (not allowed) xxx 0 b nw a ny illegal (not allowed) AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -14?103- rev.1.0 june 2016 non-wrap restrictions notes: non-wrap bl= 4 data orders shown are prohibited. mr2_device feature 2 (ma<7:0> = 02h) mr3_i/o configuration 1 (ma<7:0> = 03h) mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 02 02 h device feature2 w (rfu) rl & wl op<3:0> rl & wl (read latency & write laten- cy) write-only 0001b: rl = 3 / wl = 1 (default) 0010b: rl = 4 / wl = 2 0011b: rl = 5 / wl = 2 0100b: rl = 6 / wl = 3 0101b: rl = 7 / wl = 4 0110b: rl = 8 / wl = 4 all others: reserved mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 03 03 h i/o config-1 w (rfu) ds op<3:0> ds (drive strength) write-only 0000b: reserved 0001b: 34.3-ohm typical 0010b: 40-ohm typical (default) 0011b: 48-ohm typical 0100b: 60-ohm typical 0101b: reserved 0110b: 80-ohm typical 0111b: 120-ohm typical all others: reserved 64mb 128mb/256mb 512mb/1gb/2gb 4gb/6gb/8gb not across full page boundary x8 1fe, 1ff, 000, 001 3fe, 3ff, 000, 001 7fe, 7ff, 000, 001 ffe, fff, 000, 001 x16 fe, ff, 00, 01 1fe, 1ff, 000, 001 3fe, 3ff, 000, 001 7fe, 7ff, 000, 001 x32 7e, 7f, 00, 01 fe, ff, 00, 01 1fe, 1ff, 000, 001 3fe, 3ff, 000, 001 not across sub page boundary x8 07e, 07f, 080, 081 0fe, 0ff, 100, 101 17e, 17f, 180, 181 0fe, 0ff, 100, 101 1fe, 1ff, 200, 201 2fe, 2ff, 300, 301 1fe, 1ff, 200, 201 3fe, 3ff, 400, 401 5fe, 5ff, 600, 601 3fe, 3ff, 400, 401 7fe, 7ff, 800, 801 bfe, bff, c00, c01 x16 7e, 7f, 80, 81 0fe, 0ff, 100, 101 1fe, 1ff, 200, 201 3fe, 3ff, 400, 401 x32 none none none none AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -15?103- rev.1.0 june 2016 mr4_ device temperature (ma<7:0> = 04h) notes: 1. a mode register read from mr4 will reset op7 to ?0?. 2. op7 is reset to ?0? at power-up. 3. if op2 equals ?1?, the device temperature is greater than 85?c. 4. op7 is set to ?1?, if op2~op0 has cha nged at any time since the last read of mr4. 5. lpddr2 might not operate properly when op<2:0> = 000b or 111b. 6. for specified operating temperature range and maxi mum operating temperature. 7. lpddr2 devices must be derated by adding 1.875ns to the following core timing parameters: trcd, trc, tras, trp, and trrd. the tdqsck parameter must be derated .. prevaili ng clock frequency specifications and related setup and hold timings remain unchanged. 8. the recommended frequency for reading mr4 is provided in ?temperature sensor?. mr5_basic configuration 1 (ma<7:0> = 05h) mr6_basic configuration 2 (ma<7:0> = 06h) mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 04 04 h r tuf (rfu) refresh rate op<2:0> refresh rate read-only 000b: sdram low temperature operating limit exceeded 001b: 4x trefi, 4x trefipb, 4x trefw 010b: 2x trefi, 2x trefipb, 2x trefw 011b: 1x trefi, 1x trefipb, 1x trefw (<=85?c) 100b: reserved 101b: 0.25x trefi, 0.25x trefipb, 0.25x trefw, do not de- rate sdram ac timing 110b: 0.25x trefi, 0.25x trefipb, 0.25x trefw, de-rate sdram ac timing 111b: sdram high temperature operating limit exceeded op7 tuf (temperature update flag) read-only 0b: op<2 :0> value has not changed since last read of mr4. 1b: op<2:0> value has changed since last read of mr4. mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 05 05 h basic config-1 r lpddr2 manufacturer id op<7:0> manufacturer id read-only see jesd-tbd lpddr2 manufacturer id encodings mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 06 06 h basic config-2 r revision id1 op<7:0> revision id1 read-only reserved AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -16?103- rev.1.0 june 2016 mr7_basic configuration 3 (ma<7:0> = 07h) mr8_basic configuration 4 (ma<7:0> = 08h) mr9_test mode (ma<7:0> = 09h) mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 07 07 h basic config-3 r revision id2 op<7:0> revision id1 read-only reserved mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 08 08 h basic config-4 r i/o width density type op<1:0> type read-only 00b: s4 sdram 01b: s2 sdram 10b: n nvm 11b: reserved op<5:2> density read-only 0000b: 64mb 0001b: 128mb 0010b: 256mb 0011b: 512mb 0100b: 1gb 0101b: 2gb 0110b: 4gb 1110b: 6gb 0111b: 8gb 1000b: 16gb 1001b: 32gb all others: reserved op<7:6> i/o width read-only 00b: x32 01b: x16 10b: x8 11b: not used mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 09 09 h test mode w vendor-specific test mode op<7:0> vendor-specific test mode write-only AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -17 ? 103- rev.1.0 june 2016 mr10_calibration (ma<7:0> = 0ah) notes: 1. host processor shall not wr ite mr10 with ?reserved? values. 2. lpddr2 devices shall ignore calibration command, when a ?reserved? values is written into mr10. 3. see ac timing table for the calibration latency. 4. if zq is connected to vssca through rzq, either the zq calibration function (see ?mrw zq calibration command?) or default calibration (t hrough the zq reset command) is supported. if zq is connected to vddca, the device oper- ates with default calibrat ion, and zq calibration commands are ignored. in both cases, the zq connection must not change after power is supplied to the device. 5. devices that do not su pport calibration ignore the zq calibration command. 6. optionally, the mrw zq initialization calibration co mmand will update mr0 to indicate rzq pin connection. mr11:15_(reserved) (ma<7:0> = 0bh- 0fh) mr16_pasr_bank mask (ma<7:0> = 010h) mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 10 0a h io calibration w calibration code op<7:0> calibration code write-only 0xff: calibration command after initialization 0xab: long calibration 0x56: short calibration 0xc3: zq reset all others: reserved mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 11~15 0b h ~0f h (reserved) (rfu) op<7:0> rfu mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 16 10 h pasr_bank w bank mask op<7:0> bank mask code write-only 0b: refr esh enable to the bank (=unmasked, default) 1b: refresh blocked (=masked) AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -18?103- rev.1.0 june 2016 notes: this table indicates tha range of row addresses in each masked segment. x is don?t care for a particular seg- ment. mr17_pasr_segment mask (ma<7:0> = 011h) notes: this table indicates the range of row addresses in each masked segment. x is don?t care for a particular seg- ment. op bank mask 4 bank 8 bank 0 xxxxxxx1 bank 0 bank 0 1 xxxxxx1x bank 1 bank 1 2 xxxxx1xx bank 2 bank 2 3 xxxx1xxx bank 3 bank 3 4 xxx1xxxx - bank 4 5 xx1xxxxx - bank 5 6 x1xxxxxx - bank 6 7 1xxxxxxx - bank 7 mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 17 11 h pasr_seg w segment mask op<7:0> segment mask code write-only 0b: refres h enable to the segment (=unmasked, default) 1b: refresh blocked (=masked) segment op segment mask 1gb 2gb, 4gb 8gb r12:10 r13:11 r14:12 0 0 xxxxxxx1 000b 1 1 xxxxxx1x 001b 2 2 xxxxx1xx 010b 3 3 xxxx1xxx 011b 4 4 xxx1xxxx 100b 5 5 xx1xxxxx 101b 6 6 x1xxxxxx 110b 7 7 1xxxxxxx 111b AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -19 ? 103- rev.1.0 june 2016 mr18:19_(reserved) (ma<7:0> = 012h- 013h) mr20:31_(do not use) (ma<7:0> = 014h- 01fh) mr32_dq calibration pattern a (ma<7:0> = 020h) mr40_dq calibration pattern b(ma<7:0> = 028h) mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 18~19 12 h ~13 h (reserved) (rfu) op<7:0> rfu mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 20~31 18 h ~1f h reserved for nvm op<7:0> reserved for nvm mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 32 20 h dq calibration pattern a r see ?data calibration pattern description? op<7:0> reads to mr32 return dq calibration pattern a read-only mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 40 28 h dq calibration pattern b r see ?data calibration pattern description? op<7:0> reads to mr40 return dq calibration pattern b read-only AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -20 ? 103- rev.1.0 june 2016 mr6 3_reset (ma<7:0> = 03fh): mrw only notes: for additional informat ion on mrw reset, see ?mode register write command? on timing spec. do not use and reserved function s mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 63 3f h reset w x op<7:0> reset write-only x mr# ma<0:7> function access op7 op6 op5 op4 op3 op2 op1 op0 33~39 21 h ~27 h (do not use) 41~47 29 h ~2f h (do not use) 48~62 30 h ~3e h (reserved) (rfu) 64~126 40 h ~7e h (reserved) (rfu) 127 7f h (do not use) 128~190 80 h ~be h (reserved) (rfu) 191 bf h (do not use) 192~254 c0 h ~fe h (reserved) (rfu) 255 ff h (do not use) AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -21 ? 103- rev.1.0 june 2016 lpddr2-s4 sdram truth table operation or timing that is not specifi ed is illegal, and after such an event, in order to guarantee proper operation, the lpddr2 device must be powered down and then restarted th rough the specified initializat ion sequence before normal operation can continue. command truth table ck_t(n-1) ck_t(n) llllm a0m a1m a2 m a3m a4m a5 m a6 m a 7 op0 op1 op2 op3 op4 op5 op 6 op7 lllhm a0m a1m a2 m a3m a4m a5 m a6 m a7 llhl llhh llh l h r8 r9 r10 r11 r1 2 ba0b a1b a2 r0 r1 r 2 r3 r4 r5 r 6 r7 r13 r14 h l l rfu rfu c1 c 2 ba0b a1b a2 ap 3,4 c3 c4 c5 c 6 c7 c8 c9 c10 c11 h l h rfu rfu c1 c 2 ba0b a1b a2 ap 3,4 c3 c4 c5 c 6 c7 c8 c9 c10 c11 hhlh ab ba0b a1b a2 hhl l hhl hhh hhh x x exit pd, sref, dpd lhh x x m a int a in pd, sref, dpd (nop) l enter power down hlh lh x x x x x x nop hhh m a int a in pd, sref, dpd (nop) lll x x enter deep power down h nop hhl ll x x x x x x bst hhl hhl prech a rge (b a nk) hhl rea d (b a nk) write (b a nk) hhl activ a te (b a nk) hhl x x refresh (a ll b a nk) h enter s elf refresh hll hl l x x x x x refresh (per b a nk) 11 hhl ca9 ck edge ddr ca pins (10) mrw hhl ca5 ca6 ca7 ca8 sdr command pins ca0 ca1 ca2 cke cs_n sdram command ca 3 ca4 mrr hh AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -22 ? 103- rev.1.0 june 2016 notes: 1. all lpddr2 commands are defined by states of cs_n(cs ), ca0, ca1, ca2, ca3, and cke at the rising edge of the clock. 2. for lpddr2 sdram, bank addresses ba0, ba1, ba2 (b a) determine which bank is to be operated upon. 3. ap ?high? during a read or write command indicates th at an auto-precharge will occur to the bank associated with the read or write command. 4. ?x? means ?h or l (but a defined logic level)?. 5. self refresh exit and deep po wer down exit are asynchronous. 6. vref must be between 0 and vddq during self refresh and deep down operation. 7. caxr refers to command/address bit ?x? on the rising edge of clock. 8. caxf refers to command/address bit ?x? on the rising edge of clock. 9. cs_n(cs ) and cke are sampled at the rising edge of clock. 10. per bank refresh is only allowed in devices with 8 banks. 11. the least-significant column address c0 is not tr ansmitted on the ca bus, and is implied to be zero. cke truth table device current state * 3 cke n-1 *1 cke n *1 cs_n *2 command n *4 operation n *4 device next state notes a ctive power down llx x m a int a in a ctive power down a ctive power down l h h nop exit a ctive power down a ctive 6 , 9 idle power down llx x m a inta in idle power down idle power down l h h nop exit idle power down idle 6 , 9 resetting power down llx x m a int a in resetting power down resetting power down l h h nop exit resetting power down idle or resetting 6 , 9, 1 2 deep power down llx x m a int a in deep power down deep power down l h h nop exit deep power down power on 8 s elf refresh llx x m a inta in s elf refresh s elf refresh l h h nop exit s elf refresh idle 7, 10 b a nk(s) a ctive h l h nop enter a ctive power down a ctive power down a ll ba nks idle hlh nop enter idle power down idle power down hll enter s elf-refresh enter s elf refresh s elf refresh h l l deep power down enter deep power down deep power down resetting h l h nop enter resetting power down resetting power down h h re fer to the comm a nd truth t a ble AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -23 ? 103- rev.1.0 june 2016 notes: 1. ?cken? is the logic state of cke at clock rising edge n; ?cken-1? was the state of cke at the previous clock edge. 2. ?cs_n? is the logic state of cs_n at the clock rising edge n. 3. ?current state? is the st ate of the lpddr2 device immediately prior to clock edge n. 4. ?command n? is the command registered at clock edge n, and ?operation n? is a result of ?command n ". 5 . all states and sequences not shown are illegal or reserv ed unless explicitly described elsewhere in this document. 6 . power down exit time (txp) should elapse before a command other than nop is issued. 7 . self-refresh exit time (txsr) should elap se before a command other than nop is issued. 8 . the deep power-down exit procedure must be followed as discussed in the deep power-down section of the func- tional description. 9. the clock must toggle at least once during the txp period. 10 . the clock must toggle at least twice during the txsr time. 11 . " x" means " don' t care ". 12 . upon exiting resetting power down, the device will return to the idle state if tinit5 has expired. current state bank n - command to bank n notes: 1 . the table applies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was power down. 2 . all states and sequences not shown are illegal or reserved. 3 . current state definitions: idle: the bank or banks have been precharged, and trp has been met. active: a row in the bank has been activated, and trcd has been met. no data bursts / accesses and no register accesses are in progress. current state command operation next state notes a ny nop continue previous oper a tion current s t a te idle a cti vate s elect a nd a ctiv a te row a ctive refresh (per b ank) begin to refresh refreshing (per b a nk) 6 refresh ( a ll ba nk) begin to refresh refreshing( a ll ba nk) 7 mrw loa d v a lue to mode register mr writing 7 mrr rea d va lue from mode register idle mr re a ding reset begin device a uto-initi a liza tion resetting 7, 8 precharge dea ctiv a te row in ba nk or b a nks prech a rging 9, 15 row a ctive read s elect column, a nd st a rt re a d burst re a ding write s elect column, a nd st a rt write burst writing mrr rea d va lue from mode register a ctive mr re a ding precharge dea ctiv a te row in ba nk or b a nks prech a rging 9 rea ding read s elect column, a nd st a rt new re a d burst re a ding 10, 11 write s elect column, a nd st a rt write burst writing 10, 11, 1 2 b s t rea d burst termin a te a ctive 13 writing write s elect column, a nd st a rt new write burst writing 10, 11 read s elect column, a nd st a rt re a d burst re a ding 10, 11, 14 b s t write burst termin a te a ctive 13 power on reset begin device a uto-initi a liza tion resetting 7, 9 resetting mrr rea d va lue from mode register resetting mr re a ding AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -24?103- rev.1.0 june 2016 reading: a read bu r s t has b een initiated, with auto precha r ge disabled, and has no t yet terminated or b een terminated. writi ng: a write burst has been initiated, w ith a u to precha rge disabled , and ha s not yet terminated or been ter minated. 4. the followin g states must not be interr upted by a command issued to the same bank. nop c ommands or allowable c om-mands to the othe r bank should be issued on any clock edge occurring during these s tates. precharging: starts with the r egistration of a pr e charge command and ends when trp is met. once trp is met, the bank will be in the idle state. row activating: starts with r egistration of an activa te command and end s when trcd is me t. onc e trcd is m et, the ban k will be in the ?active? state. read w ith ap enabled: starts w ith the r e gistr ati on of the re ad command wi th auto precharg e enabled a nd ends when tr p ha s been met. once trp ha s been met, the ban k will be in the idle state. write wi th ap enabl ed: starts wi th r eg istrati on of a w rit e command with auto precharge enabled an d ends when trp has been met. once trp is met, the bank will be in the idle state. 5. the followin g states must not be interrupted by any ex ecutable comma nd; nop commands must be applied to each pos- itive clock edge during these states. refreshing (per b ank): starts wi th re gistration of an refresh (per bank) command and ends when trfcpb is met. once trfcpb is met, the bank will be in an ?idle? state. refr eshing (a l l bank): starts with registration of an re fresh (all ban k) command a nd ends wh en trfcab is met. once trfcab is m et, the device will be in an ?all banks idle? state. idle mr reading: starts with the registration of a m rr command and ends when tmrr ha s been met. once tmrr has been met, th e bank wil l be in the idle state. resetting mr reading: starts with the reg istration o f a mrr command an d e nds when tmr r has be en met. once tmrr has been met, the bank will be in the resetting state. active m r reading: st arts with the registration of a mr r c ommand and ends when tmrr has bee n me t. once tmrr has been met, the bank will be in the active state. mr writing: s tarts with the reg istrati on of a mr w co m man d and en ds when tmr w ha s be en met. once tmrw h as been met, the bank will be in the idle state. prechargi ng all: starts w ith the reg istrati on of a prec h ar ge-all com man d a nd ends w hen trp is met. once trp is met, the bank will be in the idle st ate. 6. bank-specific; requires that the bank is idle and no bursts are in progress. 7. not bank-specific; requires that all ban ks are idle and no bursts are in progress. 8. not bank-specific reset command is achi eved through mode register write command. 9. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for pre-charging. 10. a command other than nop should not be issued to the same bank while a read or write burst with auto precharge is enabled. 11. the new read or write command could be auto precharge enabled or auto precharge disabled. 12. a write command may be applied after the completion of the read burst; otherwise, a bst must be used to end the read prior to asserting a write command. 13. not bank-specific. burst terminate (bst) command affect s the most recent read/write burst started by the most recent read/write command, regardless of bank. 14. a read command may be applied after the completion of the write burst; otherwise, a bst must be used to end the write prior to asserting a read command. 15. if a precharge command is issued to a bank in the idle state, trp shall still apply. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -25?103- rev.1.0 june 2016 current state bank n - command to ba nk m notes: 1. the table applies when both cken-1 and cken are high, and after txsr or txp has been met if the previous state was s elf refr es h or p ower down. 2. a ll states and sequences not s hown are illegal or reserved. 3. current state definitions: idle: the bank has been precharged, and trp has been met. a c tive: a row in the bank has been activated, and trcd has been met. no data bur sts/acc es ses and no register accesses ar e in progress. reading: a read burst has been initiated, with auto prec harge disabled, and has not yet terminated or been terminated. wr iting: a wr ite burst has been initiated, with auto precharge dis abled, and has not yet terminated or been terminated. 4. refresh, self-refresh, and mode register write commands may only be is sued when all bank are idle. 5. a burst terminate ( bs t) command cannot be issued to another bank; it applies to the bank represented by the c urrent s tate only. 6. the following states must not be interrupted by any executable com mand; nop commands m ust be applied during each clock cycle while in these states: current state of bank n command for bank m operation next state for bank m notes a ny nop continue previous oper a tion current s t a te of b a nk m idle a ny a ny comm a nd a llowed to b a nk m - 18 row a ctiv a ting, a ctive, or prech a rging a ctiva te s elect a nd a ctiv a te row in b a nk m a ctive 7 read s elect column, a nd st a rt re a d burst from b a nk m re a ding 8 write s elect column, a nd st a rt write burst to b a nk m writing 8 precharge dea ctiv a te row in b a nk or b a nks precha rging 9 mrr rea d v a lue from mode register idle mr re a ding or a ctive mr re a ding 10, 11, 13 b s t rea d or write burst termin a te a n ongoing rea d/write from/to b a nk m a ctive 18 rea ding ( a utoprech a rge disa bled) read s elect column, a nd st a rt re a d burst from b a nk m re a ding 8 write s elect column, a nd st a rt write burst to b a nk m writing 8, 14 a ctiva te s elect a nd a ctiv a te row in b a nk m a ctive precharge dea ctiv a te row in b a nk or b a nks precha rging 9 writing ( a utoprech a rge disa bled) read s elect column, a nd st a rt re a d burst from b a nk m re a ding 8, 1 6 write s elect column, a nd st a rt write burst to b a nk m writing 8 a ctiva te s elect a nd a ctiv a te row in b a nk m a ctive precharge dea ctiv a te row in b a nk or b a nks precha rging 9 rea ding with a utoprech a rge read s elect column, a nd st a rt re a d burst from b a nk m re a ding 8, 15 write s elect column, a nd st a rt write burst to b a nk m writing 8, 14, 15 a ctiva te s elect a nd a ctiv a te row in b a nk m a ctive precharge dea ctiv a te row in b a nk or b a nks precha rging 9 writing with a utoprech a rge read s elect column, a nd st a rt re a d burst from b a nk m re a ding 8, 15, 1 6 write s elect column, a nd st a rt write burst to b a nk m writing 8, 15 a ctiva te s elect a nd a ctiv a te row in b a nk m a ctive precharge dea ctiv a te row in b a nk or b a nks precha rging 9 power on reset begin device a uto-initi a liza tion resetting 1 2 , 17 resetting mrr rea d v a lue from mode register resetting mr re a ding AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -26?103- rev.1.0 june 2016 idle mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the idle state. resetting mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the resetting state. active mr reading: starts with the registration of a mrr command and ends when tmrr has been met. once tmrr has been met, the bank will be in the active state. mr writing: starts with the registration of a mrw comman d and ends when tmrw has been met. once tmrw has been met, the bank will be in the idle state. 7. trrd must be met between activate command to ba nk n and a subsequent activate command to bank m. 8. reads or writes listed in the command column incl ude reads and writes with auto precharge enabled and reads and writes with auto precharge disabled. 9. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for pre-charging. 10. mrr is allowed during the row activating state (row acti vating starts with registration of an activate command and ends when trcd is met.) 11. mrr is allowed during the precharging state. (prechargi ng starts with registration of a precharge command and ends when trp is met. 12. not bank-specific; requires that all banks are idle and no bursts are in progress. 13. the next state for bank m depends on the current state of bank m (idle, row activating, precharging, or active). the reader shall note that the state may be in transition when a mrr is issued. th erefore, if bank m is in the row activating state and precharging, the next state may be active and precharge dependent upon trcd and trp respectively. 14. a write command may be applied after the completion of t he read burst, otherwise a bst must be issued to end the read prior to asserting a write command. 15. read with auto precharge en abled or a write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restriction. 16. a read command may be applied after the completion of the write burst; otherwise, a bst must be issued to end the write prior to asserting a read command. 17. reset command is achieved through mode register write command. 18. bst is allowed only if a read or write burst is ongoing. data mask truth table notes: 1. used to mask write data, provided coincident with the corresponding data. name (functional) dm dqs note write enable l valid 1 write inhibit h x 1 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -27?103- rev.1.0 june 2016 command d efiniti ons and timing diagrams active the active command is issued by holding cs low, ca0 low, and ca1 high at the rising edge of the clock. the bank addresses ba0-ba2 are used to select the desired bank. the row addresses r0-r14 is used to determine which row in the selected bank. the active command must be applied before any read or write oper ation can be executed. the lpddr2 sdram can accept a read or write command at time trcd after the active command is sent. once a bank has been active, it must be precharged before another active command can be applied to the same bank. the bank active and precharge times are defined as tras and trp, respectively. the minimum time interval between two successive active commands on the same bank is determined by the ras cycle time of t he device (trc). the minimum time inter- val between two successive active commands on different banks is defined by trrd. certain restriction on operation of the 8 bank devices must be observed. one for restricting the number of sequential active commands that can be issued and another for allo wing more time for ras precharge for a precharge all com- mand. the rules are as follows: 8-bank device sequential ba nk activation restriction : no more than 4 banks may be activated (or refreshed, in the case of refpb) in a rolling tfaw window. converting to clocks is done by dividing tfaw[ns] by tck[ns], and rounding up to next integer value. as an example of the rolling window, if ru{ (tfaw / tck) } is 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued at or between clock n+1 and n+9. refpb also counts as bank-activation for the purposes of tfaw. 8 bank device precharge all allowance: trp for a precharge all command for an 8 bank device shall equal to trpab, which is greater than trppb. notes: 1. a precharge-all command uses trpab timing, while a singl e bank precharge command uses trppb timing. in this figure, trp is used to denote either an al l-bank precharge or a single bank precharge. activate command cycle: trcd= 3 , trp= 3 , trrd=2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -28?103- rev.1.0 june 2016 notes: 1. exclusively for 8-bank devices. no more than 4 banks may be activated in a rolling tfaw window. command input signal timing definition notes: 1. setup and hold conditions also apply to the cke pin. tfaw timing command input setup and hold timing AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -29 ? 103- rev.1.0 june 2016 read and write access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting cs low, ca0 high, and ca1 low at the rising edge of the clock. ca2 must also be defined at this time to determine whether the access cycle is a read operation (ca2 high) or a write operation (ca2 low). the lpddr2 sdram provides a fast column access operation. a single read or write command will initiate a burst read or write operation on successive clock cycles. for lpddr2-s4 devices, a new burst access must not interrupt t he previous 4-bit burst operation, in case of bl=4 set- ting. in case of bl=8 and bl=16 settings, reads may be inte rrupted by reads, and writes may be interrupted by writes provided that this occurs on even clock cycles after the read or write command and that tccd is met. the minimum cas to cas delay is defined by tccd. burst read the burst read command is initiated by having cs low, ca0 high, ca1 low and ca2 high at the rising edge of the clock. the command address bus inputs, ca5r-ca6r and ca 1f-ca9f, determine the starting column address for the burst. the read latency (rl) is defined fr om the rising edge of the clock on which the read command is issued to the rising edge of the clock from which the tdqsck delay is measured. the first valid datum is available rl * tck + tdqsck + tdqsq after the rising edge of the clock where th e read command is issued. th e data strobe output is driven low trpre before the first rising valid strobe edge. t he first bit of the burst is sy nchronized with the first rising edge of the data strobe. each subseq uent data-out appears on each dq pin edge aligned with the data strobe. the rl is programmed in the mode registers. timings for the data strobe are measured relative to the crosspoint of dqs and its complement, dqs . notes: 1. tdqsck can span mu ltiple clock periods. 2. an effective burst length of 4 is shown. data output (read) timing (tdqsckmax) AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -30 ? 103- rev.1.0 june 2016 data output (read) timing (tdqsckmin), bl=4 burst read: rl=5, bl=4, tdqsck > tck burst read: rl= 3 , bl=8, tdqsck < tck AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -31 ? 103- rev.1.0 june 2016 notes: 1. tdqsckdlmax is defined as the maximum of abs(td qsckn - tdqsckm) for any { tdqsckn - tdqsckm} pair within any 32ms rolling window. tdqsckdl timing : tdqsckdl = |tdqsckn t tdqsckm| within any 32ms rolling window AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -32 ? 103- rev.1.0 june 2016 notes: 1. tdqsckdmmax is defined as the maximum of abs(tdqs ckn - tdqsckm) for any { tdqsckn - tdqsckm} pair within any 1.6us rolling window. tdqsckdm timing : tdqsckdm= |tdqsckn t tdqsckm| within any 1.6us rolling window AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -33?103- rev.1.0 june 2016 notes: 1. tdqsckdsmax is defined as the maximum of abs(tdqsck n - tdqsckm) for any { tdqsckn - tdqsckm} pair for reads within a consecutive burst within any 160ns rolling window. tdqsckds timing : tdqsckds = |tdqsckn t tdqsckm| within a consecutive burst within any 160ns rolling window AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -34?103- rev.1.0 june 2016 the minimum time from the burst read command to the bu rst write command is defined by the read latency (rl) and the burst length (bl). minimum read-to- write latency is rl + ru(tdqsck(max)/tck) + bl/2 + 1 - wl clock cycles. note that if a read burst is truncated with a burst termin ate (bst) command, the effective burst length of the trun- cated read burst should be used as ?bl? to calculate the minimum read-to-write delay. the seamless burst read operation is supported by enablin g a read command at every other clock cycle for bl = 4 operation, every fo urth clock cycle for bl = 8 operatio n, and every eighth clock cycle fo r bl=16 operation. this operation is supported as long as the banks are activated, whether the accesses read the same or different banks. for lpddr2-s4 devices, burst read can be interrupted by another read on even clock cycles after the read command, provided that tccd is met. for lpddr2-s2 devices, burst re ads may be interrupted by ot her reads on any subsequent clock, provided that tccd is met. burst read followed by burst write: rl= 3 , wl=1, bl=4 seamless burst read: rl= 3 , bl=4, tccd=2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -35 ? 103- rev.1.0 june 2016 notes: 1. reads can only be interrupted by other reads or the bst command. 2. the effective burst length of the first read eq uals two times the number of clock cycl es between the first read and the interrupting read. burst write the burst write command is initiated with cs low, ca0 high, ca1 low, and ca2 low at the rising edge of the clock. the command address bus inputs, ca5r-ca6r and ca 1f-ca9f, determine the starting column address for the burst. write latency (wl) is defined from the rising edge of the clock on which the write command is issued to the ris- ing edge of the clock from which the tdqss delay is measured. the first valid data must be driven wl x tck + tdqss from the rising edge of the clock from which the write command is issued. the data strobe signal (dqs) must be driven low twpre prior to data input. the burst cycle data bits must be applied to the dq pins tds prior to the associated edge of the dqs and held valid until tdh afte r that edge. burst data is sampled on successive edges of the dqs until the 4-, 8-, or 16-bit burst length is comple ted. after a burst write operation, tw r must be satisfied before a precharge command to the same bank can be issued. pin input timings are measured relative to the cross point of dqs and its complement, dqs . read burst interrupt example: rl= 3 , bl=8, t ccd=2 data input (write) timing AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -36?103- rev.1.0 june 2016 notes: 1. the minimum number of clock cycles from the burst write command to the burst read command for any bank is [wl + 1 + bl/2 + ru (twtr / tck) ]. 2. twtr starts at the rising edge of t he clock after the last valid input datum. 3. if a write burst is truncated with a burst terminate (bst ) command, the effective burst length of the truncated write burst should be used as ?bl? to calcul ate the minimum write to read delay. burst write: wl=1, bl=4 burst write followed by burst read: rl= 3 , wl=1, bl=4 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -37?103- rev.1.0 june 2016 notes: 1. the seamless burst write operation is supported by enabling a write command ev ery other clock for bl=4 operation, every four clocks for bl=8 operation, or every eight clocks for bl=16 oper ation. this operation is allowed regardless of same or different banks as long as the banks are activated. notes: 1. writes can only be interrupted by other writes or the bst command. 2. for lpddr2-s4 devices, write burst interrupt function is only allowed on burst of 8 and burst of 16. 3. for lpddr2-s4 devices, write burst interrupt may only occur on even clo ck cycles after the previous write com- mands, provided that tccd(min) is met. 4. write burst interruption is al lowed to any bank inside dram. 5. write burst with au to-precharge is not allowed to be interrupted. 6. the effective burst length of the first write equals two times the number of clock cycles between the first write and the interrupting write. seamless burst write: wl=1, bl=4, tccd=2 write burst interrupt timing: wl=1, bl=8, tccd=2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -38?103- rev.1.0 june 2016 burst terminate the bst command is initiated with cs low, ca0 high, ca1 high, ca2 low, and ca3 low at the rising edge of the clock. a bst command can only be issued to terminate an active read or write burst. therefore, a bst command can only be issued up to and including bl/2 - 1 clock cycles after a read or write command. the effective burst length of a read or write command truncated by a bst command is as follows: effective burst length = 2 x (number of clock cycles from the read or write command to the bst command). if a read or write burst is truncated with a bst comm and, to calculate the minimum read-to-write or write-to- read delay, the effective burst length of the truncat ed burst should be used as the value for bl. the bst command only affects the most recent read or write command. the bst command truncates an ongoing read burst rl x tck + tdqsck + tdqsq af ter the rising edge of the clock where the bst command is issued. the bst command truncates an on-going write burst wl x tck + tdq ss after the rising edge of the clock where the bst com- mand is issued. for lpddr2-s4 devices, the 4-bit pref etch architecture enables bst command assertion on even clock cycles following a write or read command. the effectiv e burst length of a read or write command truncated by a bst command is thus an integer multiple of 4. notes: 1. the bst command truncates an ongoing write burst wl * tck + tdqss after the rising edge of the clock where the burst terminate command is issued. 2. for lpddr2-s4 devices, bst can onl y be issued an even num ber of clock cycles after the write command. 3. additional bst commands are not allowed after t4, and ma y not be issued until after t he next read or write com- mand. burst write trunc a ted by bst: wl=1, bl=16 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -39?103- rev.1.0 june 2016 notes: 1. the bst command truncates an ongoing read burst rl * tck + tdqsck + tdqsq after the rising edge of the clock where the burst terminate command is issued. 2. for lpddr2-s4 devices, bst can onl y be issued an even num ber of clock cycles after the write command. 3. additional bst commands are not allowed after t4, and ma y not be issued until after t he next read or write com- mand. write data mask one write data mask (dm) pin for each data byte (dq) will be supported on lpddr2 devices , consistent with the imple- mentation on lpddr sdrams. each data mask (dm) may mask its respective data byte (dq) for any given cycle of the burst. data mask has identical timings on write operations as the data bits, though used as input only, is internally loaded identically to data bits to insure matched system timing. burst read truncat ed by bst: rl= 3 , bl=16 d a ta ma s k t i min g AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -40?103- rev.1.0 june 2016 notes: 1. for the data mask function, wl=2, bl=4 is shown; the second data bit is masked. precharge the precharge command is used to precharge or close a ban k that has been activated. t he precharge command is ini- tiated by having cs low, ca0 high, ca1 high, ca2 low, and ca3 hi gh at the rising edge of the clock. the pre- charge command can be used to precharge each bank indepen dently or all banks simultaneously. for 4-bank devices, the ab flag, and the bank address bits, ba0 and ba1, are us ed to determine which bank(s) to precharge. for 8-bank devices, the ab flag, and the bank address bits, ba0, ba1, an d ba2, are used to determine which bank(s) to precharge. the bank(s) will be available for a subsequent row access tr pab after an all-bank precharge command is issued and trppb after a single-bank precharge command is issued. in order to ensure that 8-bank devices do not exceed the instantaneous current supplying capability of 4-bank devices, the row precharge time (trp) for an all-bank precharge for 8-bank devices (trpab) will be longer than the row pre- charge time for a single-bank precharge (trppb). for 4-bank devices, the row precharge time (trp) for an all-bank precharge (trpab) is equal to the row prechar ge time for a single-bank precharge (trppb). write data mask: wl=2, bl=4, second dq masked AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -41 ? 103- rev.1.0 june 2016 bank selec tion for precharge by address bits burst read followed by precharge for the earliest possible precharge, th e precharge command may be issued bl/2 clock cycles after a read command. a new bank active (command) may be issued to the same ba nk after the row precharge time (trp). a precharge com- mand can not be issued until after tras is satisfied. for lpddr2-s4 devices, the minimum read to precharge spac ing has also to satisfy a minimum analog time from the rising cloak edge that initiates the last 4-bit precharge of a read command. this time is called trtp (read to pre- charge). for lpddr2-s4 devices, trtp begins bl/2 - 2 clock cycles after the read command. if the burst is truncated by a bst command, the effective ?bl? ahsll be used to calculate when trtp begins. ab (ca4r) ba2 (ca9r) ba1 (ca8r) ba0 (ca7r) precharged bank(s) 4-bank device precharged bank(s) 8-bank device 0 0 0 0 bank 0 only bank 0 only 0 0 0 1 bank 1 only bank 1 only 0 0 1 0 bank 2 only bank 2 only 0 0 1 1 bank 3 only bank 3 only 0 1 0 0 bank 0 only bank 4 only 0 1 0 1 bank 1 only bank 5 only 0 1 1 0 bank 2 only bank 6 only 0 1 1 1 bank 3 only bank 7 only 1 don?t care don?t care don? t care all banks all banks burst read followe d by precharge: rl= 3 , bl=8, ru( t rtp(min)/ t ck)=2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -42 ? 103- rev.1.0 june 2016 burst write followed by precharge for write cycles, a delay must be satisfie d from the time of the la st valid burst input data until the precharge command may be issued. this delay is known as the write recovery ti me (twr) referenced from the co mpletion of the burst write to the precharge command. no precharge command to the same bank should be issued prior to the twr delay. lpddr2-s2 devices write data to the array in prefetch pair s (prefetch = 2) and lpddr2-s4 devices write data to the array in prefetch quadruples (prefetch = 4). the beginning of an internal write operation may only begin after a prefetch group has been completely. therefore, the write recovery time (twr) starts different boundaries for lpddr2-s2 and lpddr2-s4 devices. for lpddr2-s2 devices, minimum write to precharge comma nd spacing to the same bank is wl + ru(bl/2) + 1 + ru(twr/tck) clock cycles. for lpddr2-s4 devices, minimum wr ite to precharge command spacing to the same bank is wl + bl/2 + 1+ ru (twr/tck) clock cycles. for an untrunca ted burst, bl is the value fr om the mode register. for a truncated burst, bl is t he effective burst length. burst read followed by precharge: rl= 3 , bl=4, ru( t rtp(min)/ t ck) = 3 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -43 ? 103- rev.1.0 june 2016 auto precharge before a new row in an active bank can be opened, the ac tive bank must be precharged using either the precharge command or the auto-precharge function . when a read or a write command is given to the lpddr2 sdram, the ap bit (ca0f) may be set to allow the active bank to automatic ally begin precharge at the earliest possible moment during the burst read or write cycle. if ap is low when the read or write command is issued, the normal read or write burst operation is executed and the bank remains active at the comp letion of the burst. if ap is high when the read or write command is issued, then the auto-precharge function is enga ged. this feature allows the precharge operation to be par- tially or completely hidden during burst read cycles (depen dent upon read or write laten cy) thus improving system per- formance for random data access. burst read with auto precharge if ap (ca0f) is high when a read command is issued, the read with auto-precharge function is engaged. lpddr2- s4 devices start an auto-precharge operation on the rising edge of the clock bl/2 or bl/2 - 2 + ru(trtp/tck) clock cycles later than the read with ap command, whichever is greater. a new bank activate command may be issued to the same bank if both of the following two conditions are satisfied simultaneously: the ras precharge time (trp) has been satisfied fr om the clock at which t he auto-precharge begins. the ras cycle time (trc) from the previ ous bank activation has been satisfied. burst write followed by precharge: wl=1, bl=4 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -44 ? 103- rev.1.0 june 2016 burst write with auto precharge if ap (ca0f) is high when a write command is issued, the write with auto-precharge function is engaged. the lpddr2 sdram starts an auto-precharge operation on the rising edge which is twr cycles after the completion of the burst write. a new bank activate command may be issued to the same bank if both of the following two conditions are satisfied: the ras precharge time (trp) has been satisfied fr om the clock at which the auto-precharge begins. the ras cycle time (trc) from the previous bank activation has been satisfied. burst read with aut o -precharge: rl= 3 , bl=4, ru( t rtp(min)/ t ck)=2 burst write with auto-precharge: wl=1, bl=4 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -45 ? 103- rev.1.0 june 2016 lpddr2-s4: precharge & auto prech arge clarific ation notes: 1. for a given bank, the precharge period should be counted from the latest precharge co mmand, either one bank pre- charge or precharge all, issued to that bank. the prechar ge period is satisfied after trp depending on the latest pre- charge command issued to that bank. 2. any command issued during the minimum delay time as specified above table is illegal. 3. after read with ap, seamless read o perations to different banks are supported. after write with ap, seamless write operations to different banks are supp orted. read w/ap and write a/ap may not be interrupted or truncated. from command to command minimum delay between ?from command? to ?t o command? unit notes read precharge (to same bank as read) bl/2 + max(2, ru(trtp/tck)) - 2 clks 1 precharge all bl/2 + max(2, ru(trtp/tck)) - 2 clks 1 bst (for reads) precharge (to same bank as read) 1 clks 1 precharge all 1 clks 1 read w/ap precharge (to same bank as read w/ap) bl/2 + max(2, ru(trtp/tck)) - 2 clks 1,2 precharge all bl/2 + max(2, ru(trtp/tck)) - 2 clks 1 activate (to same bank as read w/ap) bl/2 + max(2, ru(trtp/tck)) - 2 + r u(trppb/tck) clks 1 write or write w/ap (same bank) illegal clks 3 write or write w/ap (different bank) rl + bl/2+ ru(tdqsckmax/tck) - wl + 1 clks 3 read or read w/ap (same bank) illegal clks 3 read or read w/ap (different bank) bl/2 clks 3 write precharge (to same bank as write) wl + bl/2 + ru(twr/tck) + 1 clks 1 precharge all wl + bl/2 + ru(twr/tck) + 1 clks 1 bst (for writes) precharge (to same bank as write) wl + ru(twr/tck) + 1 clks 1 precharge all wl + ru(twr/tck) + 1 clks 1 write w/ap precharge (to same bank as write w/ap) wl + bl/2 + ru(twr/tck) + 1 clks 1 precharge all wl + bl/2 + ru(twr/tck) + 1 clks 1 activate (to same bank as write w/ap) wl + bl/2 + ru(twr/tck) + 1 + r u(trppb/tck) clks 1 write or write w/ap (same bank) illegal clks 3 write or write w/ap (different bank) bl/2 clks 3 read or read w/ap (same bank) illegal clks 3 read or read w/ap (different bank) wl + bl/2 + ru(twtr/tck) + 1 clks 3 precharge precharge (to same bank as precharge) 1 clks 1 precharge all 1 clks 1 precharge all precharge 1 clks 1 precharge all 1 clks 1 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -46?103- rev.1.0 june 2016 refresh command the refresh command is initiated by having cs low, ca0 low, ca1 low, and ca2 hi gh at the rising edge of clock. per bank refresh is initiated by having ca3 low at the rising edge of the clock and all bank refresh is initiated by hav- ing ca3 high at the rising edge of clock. per bank refresh is only allowed in devices with 8 banks. a per bank refresh command, refpb performs a refresh opera tion to the bank which is scheduled by the bank counter in the memory device. the bank sequence of per bank refres h is fixed to be a sequential round-robin: ?0-1-2-3-4-5-6-7- 0-1-...?. the bank count is synchronized between the contro ller and the sdram upon issuing a reset command or at every exit from self refresh, by resett ing bank count to zero. the bank addressing for the per bank refresh count is the same as established in the single-bank precharge command. a bank must be idle before it can be refreshed. it is the re sponsibility of the controller to track the bank being refreshed by the per bank refresh command. the refpb command may not be issued to the memory until the following condi- tions are met: - trfcab has been satisfied after the prior refab command. - trfcpb has been satisfied after the prior refpb command. - trp has been satisfied after the prior precharge command to that given bank. trrd has been satisfied after the prior activate command (if a pplicable, for example after activating a row in a different bank than affected by the refpb command. the target bank is inaccessible during the per bank refresh cycle (trfcpb), however other banks within the device are accessi ble and may be addressed during the per bank refresh cycle. during the refpb operation, any of the banks other th an the one being refreshed can be maintained in active state or accessed by a read or a write command. when the per bank refresh cycle has complete d, the affected bank will be in the idle state. as shown in the table, after issuing refpb: - trfcpb must be satisfied bef ore issuing a refab command. - trfcpb must be satisfied before issuing an active command to a same bank. - trrd must be satisfied before issuin g an active command to a different bank. - trfcpb must be satisfied before issuing another refpb command. an all bank refresh command, refab performs a refresh opera tion to all banks. all banks have to be in idle state when refab is issued (for instance, by precharge all bank comm and). refab also synchronizes the bank count between the controller and the sdram to zero. as shown in the table, the refab command may not be issued to the memory until the following conditions have been met: - trfcab has been satisfied after the prior refab command. - trfcpb has been satisfied after the prior refpb command. - trp has been satisfied after the prior precharge commands. when the all bank refresh cycle has completed, all banks will be in the idle state. as shown in the table, after issuing refab: - the trfcab latency must be satisfied before issuing an activate command. - the trfcab latency must be satisfied before issuing a refab or refpb command. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -47?103- rev.1.0 june 2016 command scheduling se parations r elate d to ref resh notes: 1. a bank must be in the idle state before it is refreshed. therefore, after ac tivate, refab is not allowed and refpb is allowed only if it affects a bank which is in the idle state. refresh requirement (1) minimum number of refresh commands: lpddr2 requires a minimum number, r, of refresh (ref ab) commands within any rolling refresh window (trefw = 32 ms @ mr4[2:0] = 011 or tc =< 85?c). for actual values pe r density, and the resulting average refresh interval (trefi) is given in the table below. and see mode register 4 information for trefw and tr efi refresh multipliers at different mr4 settings. for devices supporting per-bank refresh, a refab command can be replaced by a full cycle of eight refpb com- mands. symbol minimum delay from to notes trfcab refab refab activate cmd to any bank refpb trfcpb refpb refab activate cmd to same bank as refpb refpb trrd refpb activate cmd to different bank than refpb activate refpb affecting an idle bank (different bank than activate) 1 activate cmd to different bank than prior activate symbol parameter 4gb(single die) 8gb(dual dies) unit number of banks 8 trefw refresh window: tcase =< 85?c 32 ms trefw refresh window: 85?c < tcase =< 105?c 8 ms r required number of refresh commands (min) 8192 8192 trefi average time between refresh commands (for reference only) tcase <= 85?c 3.9 3.9 us trefipb 0.4875 0.4875 us trfcab refresh cycle time 130 130 ns trfcpb per-bank refresh cycle time 60 60 ns trefbw burst refresh window = 4 x 8 x trfcab 4.16 4.16 us AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -48?103- rev.1.0 june 2016 (2) burst refresh limitation: t o limit maximum current consumption, a maximum of 8 refab commands may be issued in any rolling trefbw (trefbw = 4 x 8 x trfcab). this condition does not apply if refpb commands are used. (3) refresh requirements and self-refresh: if any time within a refresh window is spent in self-refresh mode, the number of required refresh commands in this par- ticular window is reduced to: r*=r -ru{tsrf/trefi} =r-ru{r*tsrf/trefw }, where ru stands for the round-up function. note: above examples are several cases on how to tsrf is calculated 1. (example a): time in self refresh mode is fully enclosed in the refresh window (trefw). 2. (example b): at self refresh entry. 3. (example c): at self refresh exit. 4. (example d): several interv als in self refresh during one trefw interv al. in this example, tsrf = tsrf1 + tsrf2. the lpddr2 devices provide significant flexibility in scheduling refresh commands as long as the boundary condi- tions are met. in the most straightforward implementations , a refresh command should be scheduled every trefi. in this case, self refresh can be entered at any time. users may choose to deviate from this regular refresh patter n, for example, to enable a period where no refreshes are required. in the extreme (e.g ., lpddr2-s4 1gb), the user can choose to issue a refresh burst of 4096 refresh com- mands at the maximum supported rate ( limited by trefbw), followed by an extended period without issuing any refresh commands, until the refresh window is comp lete. the maximum supported time without refresh com- mands is calculated as follows: trefw - (r/8) x trefbw = trefw - r x 4 x trfcab. lpddr2 s4: definit ion of tsrf AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -49?103- rev.1.0 june 2016 for example, a 1gb lpddr2-s4 device at tc =< 85?c ca n be operated without refresh commands up to 32ms - 4096 x 4 x 130ns ~ 30 ms. both the regular and the burst/paus e patterns can satisfy refresh requirements if they are repeated in every 32ms window. it is critical to satisfy the refresh requirement in every rolling refresh window during refresh pattern transitions. the supported transition from a burst pattern to a regular distribut ed pattern. if this transition occurs immediately after the burst refresh phase, all rolling trefw intervals will meet the minimum required number of refreshes. a non-supported transition - in this example, the regular refr esh pattern starts after the completion of the pause phase of the burst/pause refresh pattern. for several rolling trefw intervals, the minimum number of refresh commands is not satisfied. understanding this pattern transition is extremely important, even when only one pattern is employed. in self refresh mode, a regular distributed-refr esh pattern must be assumed. it is reco mmended entering self refresh mode immedi- ately following the burst phase of a burst /pause refresh pattern; upon exiting self refresh, begin with the burst phase. notes: 1. compared to repetitive burst refresh with subsequent refresh pause. 2. as an example, in a 1gb lpddr2-s4 device at tc =< 85?c, the distributed refresh pattern has one refresh com- mand per 7.8us; the burst refresh pa ttern has one refresh command per 0.52us, followed by ~30ms without any refresh command. regular, distributed refresh pattern AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -50?103- rev.1.0 june 2016 notes: 1. shown with subsequent refresh pause to regular, distributed-refresh pattern. 2. as an example, in a 1gb lpddr2-s4 device at tc =< 85?c, the distributed refresh pattern has one refresh com- mand per 7.8us; the burst refresh pa ttern has one refresh command per 0.52us, followed by ~30ms without any refresh command. supported transition from repetitive burst refresh AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -51?103- rev.1.0 june 2016 notes: 1. in conjunction with a burst/pause refresh pattern. recommended self refresh entr y and exit AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -52 ? 103- rev.1.0 june 2016 notes: 1. in the beginning of this example, the refpb bank is pointing to bank 0. 2. operations to other banks than the bank bei ng refreshed are allowed during the trefpb period. all bank refresh operation per-bank refresh operation n AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -53 ? 103- rev.1.0 june 2016 self refresh operation the self refresh command can be used to retain data in t he lpddr2 sdram, even if the re st of the system is powered down. when in the self refresh mode, the lpddr2 sdra m retains data without external clocking. the lpddr2 sdram device has a built-in timer to accommodate self refr esh operation. the self refr esh command is defined by having cke low, cs low, ca0 low, ca1 low, and ca2 high at th e rising edge of the clock. cke must be high during the previous clock cycle. a nop command must be driven in the clock cycle following the po wer-down command. once the command is registered, cke must be held low to keep the device in self refresh mode. lpddr2-s4 devices can operate in self refresh in both the standard or extended te mperature ranges. lpddr2-s4 devices will also manage self refresh power consumption when the operating temperature changes, lower at low tem- perature and higher at high temperature. once the lpddr2 sdram has entered self refresh mode, all of the external signals except cke, are ?don?t care?. for proper self refresh operation, power supply pins (vdd1 , vdd2, and vddca) must be at valid levels. vddq may be turned off during self-refresh. prior to exiting self-refresh , vddq must be within specifi ed limits. vrefqd and vrefca may be at any level within minimum and maximum levels. howe ver prior to exiting self-refresh, vrefdq and vrefca must be within specified limits. the sdram initiates a mini mum of one all-bank refresh command internally within tck- esr period, once it enters self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the lpddr2 sdram must remain in self refresh mode is tckesr. the user may change the external clock frequency or halt the external clock one clo ck after self refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. the procedure for exiting self refresh requires a sequence of commands. first, the clock shall be stable and within specified limits for a minimum of 2 clock cycles prior to cke going back high. once self refresh exit is registered, a delay of at least txsr must be satisfied before a valid comm and can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self refresh exit period txsr for proper operation except for self refresh re-entry. nop commands must be registered on each positive clock edge during the self refresh exit inter- val txsr. the use of self refresh mode introduces the possibility that an internally tim ed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, it is required that at least one refresh command (8 per-bank or 1 all-bank) is issued befo re entry into a subsequent self refresh. self refresh operation AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -54 ? 103- rev.1.0 june 2016 notes: 1. input clock frequency may be changed or s topped during self-refresh, provided that upon exiting self-refresh, a minimum of 2 clocks (tinit2) of stable clo ck are provided and the clock frequency is between the minimum and maximum frequency for the par tic ular speed grade. 2. device must be in the ? all banks idle? state prior to entering self refresh mode. 3. tx s r begins at the rising edge of the clock after cke is driven high. 4. a valid c om mand may be issued only after txsr is satisfied. nops shall be issued during txs r. partial array self-refresh: bank masking lpddr2-s4 sdram has 4 or 8 banks. for lpddr2-s4 devices, 64mb to 512mb lpddr2 sdram has 4 banks, while 1gb and higher density has 8. each bank of lpddr2 sdram c an be independently configured whether a self refresh operation is taking place. one mode regi ster unit of 8 bits accessible via mrw command is assigned to program the bank masking status of each bank up to 8 banks. for bank masking bit assignments, see mode register 16. the mask bit to the bank controls a refres h operation of entire memory within the ba nk. if a bank is masked via mrw, a refresh operation to entire bank is not blocked and data retent ion by a bank is not guaranteed in self refresh mode. to enable a refresh operation to a bank, a coupled mask bit has to be programmed, ?unmasked?. when a bank mask bit is unmasked, the array space being refreshed within that bank is determinate by the progra mmed status of the segment mask bit. partial array self-refresh: segment masking segment programming segment mask bits is similar to pr ogramming bank mask bits. for densities 1gb and higher, 8 segments are used for masking. mode register 17 is used for programming segment mask bits up to 8 bits. for densities less than 1gb, segment ma sking is not supported. when the mask bit to an address range (represented as a segment) is programmed as ?masked? a refresh operation to that segment is blocked. conversely, when a segment ma sk bit to an address range is unmasked, refresh to that seg- ment is enabled. a segment-masking scheme can be used in place of or in combination with a bank masking scheme in lpddr2-s4 sdram. each segment-mask bit setting is applied across all banks. notes: 1. this table illustrates an example of an 8-bank lpddr2-s 4 device, when a refresh operation to bank 1 and bank 7, as well as segment 2 and segment 7 are masked. segment mask (mr17) bnak 0 bank 1 bank 2 bank 3 bnak 4 bank 5 bank 6 bank 7 bank mask (mr16) 01000001 segment 0 0m m segment 1 0m m segment 2 1 mmmmmmmm segment 3 0m m segment 4 0m m segment 5 0m m segment 6 0m m segment 7 1 mmmmmmmm example of bank and segment masking use in lp ddr2-s4 devices AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -55?103- rev.1.0 june 2016 mode register read command the mode register read command is used to read configur ation and status data from mode registers for lpddr sdram. the mode register read (mrr) command is initiated by having cs low, ca0 low, ca1 low, ca2 low, and ca3 high at the rising edge of the clock. the mode register is selected by {ca1f-ca0f, ca9r-ca4r}. the mode reg- ister contents are available on the first data beat of dq0- dq7, rl * tck + tdqsck + tdqsq after the rising edge of the clock where the mode register read command is issued. s ubsequent data beats contain valid, but undefined content, except in the case of the dq calibrat ion function dqc, where subs equent data beats contain valid content as described in ?dq calibration?. all dqs shall be toggled for the duration of the mode register read burst. the mrr command has a burst length of four. the mode register read operation (consisting of the mrr command and the corresponding data traffic) shall not be interrupted. the mrr command period (t mrr) is 2 clock cycles. mode register reads to reserved and write-only registers shall return valid, but u ndefined content on all data beats and dqs shall be toggled. notes: 1. mode register read has a burst length of four. 2. mode register read operation shall not be interrupted. 3. mrrs to dq calibration registers mr32 and mr40 are described in ?dq calibration?. 4. only the nop command is supported during tmrr. 5. mode register data is valid only on dq[7:0] on the fi rst beat. subsequent beats contain valid but undefined data. dq[max:8] contain valid but undefined da ta for the duration of the mrr burst. 6. minimum mode register read to write latency is rl+ru(tdqsck,max/tck)+4 /2+1-wl clock cycles. 7. minimum mode register read to mode register write latency is rl+r u(tdqsck,max/tck)+4/2+1 clock cycles. after a prior read command, the mrr co mmand must not be issued ear lier than bl/2 clock cycl es, or wl + 1 + bl/2 + ru(twtr/tck) clock cycles after a prior write command, as read bursts and write bursts must not be truncated by mrr. note that if a read or write bur st is truncated with a bst command, the effective burst le ngth of the truncated burst should be used for the value bl. mode register read timing example: rl= 3 , tmrr=2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -56 ? 103- rev.1.0 june 2016 notes: 1. the minimum number of clocks from the burst read command to the mode register read command is bl/2. 2. only the nop command is supported during tmrr. notes: 1. the minimum number of clock cycles from the burst writ e command to the mode register read command is [wl + 1 + bl/2 + ru( twtr/tck)]. 2. only the nop command is supported during tmrr. read to mrr timi ng exa mple: rl= 3 , tmrr=2 burst write follo w ed by mrr: rl= 3 , wl=1, bl=4 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -57?103- rev.1.0 june 2016 temperature sensor lpddr2 devices feature a temper ature sensor whose status can be read from mr4. this sensor can be used to deter- mine an appropriate refresh rate, determine whether ac timing derating is required in t he extended temper ature range, and/or monitor the operating temperature. either the temperature sensor or the device oper ating temperature can be used to determine if operating tem perature requirements are being met. temperature sensor data may be read from mr4 using the mode register read protocol. when using the temperature sensor, the actual device case temperature may be higher than the operating temperature specification that applies for the st andard or extended temperat ure ranges. for example, tcase could be above 85?c when mr4[2:0] equals 011b. to assure proper operation using the temperature sensor, applications must a ccommodate the specific ations shown in bellow. these devices accommodate the 2 degree celsius temperature margin between the point at which the device tempera- ture enters the extended temperature range and point at whic h the controller re-configures the system accordingly. to determine the required mr4 polling frequency, the system must use the maximum tempgradient and the maximum response time of the system using the following equation: tempgradient x (readinterval + ttsi + sysrespdelay) =< 2?c for example, if tempgradient is 10 ?c/s and the sysrespdelay is 1ms: 10?c/s x (readinterval + 32ms + 1ms) =< 2?c in this case, readinterval shall be no greater than 167 ms. parameter symbol max/min value unit notes system temperature gradient tempgradient max syste m dependent c/s maximum temperature gradient experi- enced by the memory device at the tem- perature of interest over a range of 2?c. mr4 read interval readinterval max system dependent ms time period between mr4 reads from the system. temperature sensor interval ttsi max 32 ms maximum delay between internal updates of system response delay sysrespd elay max system dependent ms maximum response time from an mr4 read to the system response. device temperature margin tempmargin max 2 c margin above maximum temperature to support controller response. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -58 ? 103- rev.1.0 june 2016 dq calibration lpddr2 devices feature a dq calibration f unction that outputs one of two prede fined system-timing calibration patterns. mrr to mr32 (pattern a) or mrr to mr 40 (pattern b) will return the specified pattern on dq0 and dq8 for x16 devices and dq0, dq8, dq16, and dq24 for x32 devices. for x16 dev ices, dq[7:1] and dq[15:9] dr ive the same information as dq0 during the mrr burst. for x32 devices, dq[7:1], dq[15: 9], dq[23:17], and dq[31:25] drive the same information as dq0 during the mrr burst. m rr dq calibration commands can occur only in the idle state. data calibration pa ttern description bit time 0 bit time 1 bit time 2 bit time 3 pattern ?a? (mr32) 10 10 pattern ?b? (mr40) 00 11 temp sensor timing AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -59 ? 103- rev.1.0 june 2016 notes: only the nop command is supported during tmrr . mode register read has bl4 and shall not be interrupted. mode register write command the mrw command is used to write configuration data to mode registers. the mrw command is initiated with cs low, ca0 low, ca1 low, ca2 low, and ca3 lo w at the rising edge of the clock. th e mode register is selected by ca1f- ca0f, ca9r-ca4r. the data to be written to the mode regist er is contained in ca9f-ca2f. the mrw command period is defined by tmrw. mode register writes to read-only regist ers have no impact on the functionality of the device. dq mr 3 2 and mr40 d q calibration timing, example: rl= 3 , t mrr=2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -60 ? 103- rev.1.0 june 2016 notes: 1. only the nop command is supported during tmrw. 2. at time ty, the device is in the idle state. the mrw can only be issued when all banks are in the idle precharge state. one method of ensuring that the banks are in this state is to issue a precharge-all command. truth table for mode register read (mrr) and mode register write (mrw) mode register write reset (mrw reset) the mrw reset command br ings the device to the device auto-initialization (resetting) st ate in the power-on initializa- tion sequence. the mrw reset command can be issued from th e idle state. this command resets all mode registers to their default values. only the nop command is supported during tinit4. after mrw reset, boot timings must be observed until the device initialization sequence is complete and the device is in the idle state. array data is undefined after the mrw reset command. current stat command intermediate state next state all banks idle mrr mode register reading (all banks idle) all banks idle mrw mode register writing (all banks idle) all banks idle mrw (reset) restting (device auto-init) all banks idle bank(s) active mrr mode register reading (bank(s) idle) bank(s) active mrw not allowed not allowed mrw (reset) not allowed not allowed mode re g ister write timin g, exam p le: rl= 3 , tmrw=5 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -61 ? 103- rev.1.0 june 2016 mode register write zq calibration command the mrw command is used to initiate the zq calibration comm and. this command is used to calibrate the output driver impedance across process, temperat ure, and voltage. lpddr2-s4 devices support zq calibration. there are four zq calibration commands and related timings: tz qinit, tzqreset, tzqcl, and tzq cs. tzqinit is for initializa- tion calibration; tzqreset is for resettin g zq to the default output im pedance; tzqcl is for long calibration(s); and tzqcs is for short calibration(s). the initialization zq calibration (zqi nit) must be performed for lpddr2-s4. zqinit provides an output impedance accuracy of +/-15 percent. after initialization, the zq calibration long (zqcl) can be used to recalibrate th e system to an output impedance accuracy of +/-15 percent. a zq calibration short (zqcs) can be used periodically to compensate for temperature and voltage drift in the system. the zq reset command (zqreset) resets the output impedance calibration to a default accuracy of +/-30% across process, voltage, and temperature. this command is used to ensure output impedance accuracy to +/-30% when zqcs and zqcl commands are not used. one zqcs command can effectively correct at least 1.5% (zq correction) of output impedance errors within tzqcs for all speed bins, assuming the maximum sensitivities specified are met. the ap propriate interval between zqcs com- mands can be determined from using thes e tables and system-specific parameters. lpddr2 devices are subject to temperature drift rate (tdriftrate) and voltage drift rate (vdriftrate) in various applications. to accommodate drift rates and calculate the necessary in terval between zqcs commands, apply the following for- mula: zqcorrection ---------------------------------------------------- (tsens x tdriftrate) + (vsens x vdriftrate) where tsens = max(drondt) and vsens = max(drondv), def ine the lpddr2 temperature and voltage sensitivities. for example, if tsens = 0.75% / c, vsens = 0.20% / mv, tdriftrate = 1 c / sec and vdriftrate = 15 mv / sec, then the inter- val between zqcs commands is calculated as: 1.5 ----------------------------- = 0.4s (0.75 x 1) + (0.20 x 15) for lpddr2-s4 devices, a zq calibration command may only be issued when the device is in idle state with all banks precharged. no other activities can be performed on the lpddr2 data bus during the calibration period (tzqinit, tzqcl, tzqcs). the quiet time on the lpddr2 data bus helps to accurately calibrate ron. there is no required quiet time after the zq reset command. if multiple devices share a single zq resistor, only one device may be calibrating at any given time. after calibration is achieved, the lpddr2 device shal l disable the zq ball?s current consumption path to reduce power. in systems that share the zq resistor betw een devices, the cont roller must not allow overlap of tzqinit, tzqcs, or tzqcl between the devices. zq reset overlap is allowed. if the zq resistor is absent from the system, zq shall be connected permanently to vddca. in this case, the lpddr2 shall ignore zq calibration commands and the device will use the default calibration settings. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -62 ? 103- rev.1.0 june 2016 notes: 1. only the nop command is su pported during zq calibration. 2. cke must be registered high cont inuously during the calibration period. 3. all devices connected to the dq bus sh ould be high-z during the calibration process. zq external resistor value, tolerance and capacitive loading to use the zq calibration function, a 240 ohm +/- 1% toleranc e external resistor must be connected between the zq pin and ground. a single resistor can be used for each lpdd r2 device or one resistor can be shared between multiple lpddr2 devices if the zq calibration timings for each lpddr2 device do not overlap. the total capacitive loading on the zq pin must be limited. zq calibration initialization timing example AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -63 ? 103- rev.1.0 june 2016 power down power-down is entered synchronously when cke is registered low and cs is high at the rising edge of clock. cke must be registered high in the previ ous clock cycle. a nop command must be driven in the clock cycle following the power-down command. cke must not go low while mrr, mrw, read, or write operations are in progress. cke can go low while any other operations such as row acti vation, precharge, auto precharge, or refresh are in progress, but the power-down idd specif ication will not be applied until such operations are complete. power-down entry and exit are shown in below timing diagram. if power-down occurs when all banks are idle, this mode is re ferred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding ck, ck , and cke. in power-down mode, cke must be held low; all other input signals are ?don?t care .? cke low must be maintained until tcke is satisfied. vrefca must be maintained at a valid level during power-down. vddq can be turned off during power-down. if vddq is turn ed off, vrefdq must also be turned off. prior to exiting power-down, both vddq and vrefdq must be within their respective minimum/maximum operating ranges. no refresh operations are performed in power-down mode. the maximum duration in power-down mode is only limited by the refresh requirements outli ned in section ?refresh command?. the power-down state is excited when cke is registered high. the co ntroller must drive cs high in conjunction with cke high when exiting the power-down state. cke high must be maintained until tcke is satisfied. a valid, executable command can be applied with power-down exit latency txp after cke goes high. notes: input clock frequency can be changed or the input clock stopped during power-down, provided that the clock fre- quency is between the minimum and maximum specified freque ncies for the speed grade in use, and that prior to power-down exit, a minimum of 2 stable clocks complete. basic power-down entry and exit timing AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -64 ? 103- rev.1.0 june 2016 notes: 1. the pattern shown above can repeat over a long period of time. with this pattern, lpddr2 sdram guarantees all ac and dc timing & voltage specifications with temperature and voltage drift ensured. cke intensive environment ref to ref timing in cke intensive environment AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -65 ? 103- rev.1.0 june 2016 notes: 1. cke must be held high unt il the end of the burst operation. 2. cke may be registered lo w rl + ru(tdqsck(max)/tck) + bl/2 + 1 clo ck cycles after the clock on which the read command is registered. read to power-down entry AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -66?103- rev.1.0 june 2016 notes: 1. cke must be held high unt il the end of the burst operation. 2. cke can be registered low at rl + ru(tdqsck/tck)+ bl/2 + 1 clock cycles after the clock on which the read com- mand is registered. 3. bl/2 with trtp = 7.5ns and tras (min) is satisfied. 4. start internal precharge. read with auto-precharge to power-down entry AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -67?103- rev.1.0 june 2016 notes: 5. cke can be registered low at wl + 1 + bl/2 + ru(twr/tck) clock cycles after the clock on which the write com- mand is registered. write to power-down entry AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -68 ? 103- rev.1.0 june 2016 notes: 1. cke may be registered low wl + 1 + bl/2 + ru(twr/tck) +1 clock cycles after the wr ite command is registered. 2. start internal precharge. write with auto-precharge to power-down entry n AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -69 ? 103- rev.1.0 june 2016 refresh command to power-down entry notes: 1. cke may go low t ihcke after the clock on which the refresh command is registered. activate command to power-down entry notes: 1. cke may go low t ihcke after the clock on which the activate command is registered. precharge command to power-down entry notes: 1. cke may go low t ihcke after the clock on which the precharge command is registered. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -70 ? 103- rev.1.0 june 2016 mode register read to power-down entry notes: 1. cke may be registered low rl + ru( t dqsck/ t ck)+ bl/2 + 1 clock cycles after the clock on which the mode register read command is registered. mode register write to power-down entry notes: 6. cke may be registered low t mrw after the clock on which the mode register write command is registered. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -71 ? 103- rev.1.0 june 2016 deep power down deep power-down is entered when cke is registered low with cs low, ca0 high, ca1 high, and ca2 low at the rising edge of clock. a nop command must be driven in th e clock cycle following the power-down command. cke is not allowed to go low while mode register, read, or write operations are in progress. all banks must be in idle state with no activity on the data bus prior to entering the deep power down mode. during deep power-down, cke must be held low. in deep power-down mode, all input buffers except cke, all ou tput buffers, and the power supply to internal circuitry may be disabled within the sdram. all power supplies must be within specified limits prior to exiting deep power-down. vrefdq and vrefca may be at any level within minimum and maximum levels. however prior to exiting deep power- down, vref must be within specified limits. the contents of the sdram may be lost upon entry into deep power-down mode. the deep power-down state is exited when cke is registered high, while meeting tiscke with a stable clock input. the sdram must be fully re-initialized as described in the powe r up initialization sequence. the sdram is ready for normal operation after the initialization sequence. notes: 1. initialization sequence may start at any time after tx + 1. 2. tinit3 and tx + 1 and refer to timings in the initialization sequence. 3. the clock is stable and within specified limits for a mi nimum of 2 clock cycles prior to deep power down exit and the clock frequency is between the minimum and maximu m frequency for the particular speed grade. deep power-down entry and exit timing diagram AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -72?103- rev.1.0 june 2016 input clock stop and frequency change lpddr2 devices support input clock frequency chang e during cke low under the following conditions: - tck(abs)min is met for each clock cycle - refresh requirement apply during clock frequency change - during clock frequency change, only refab or refpb commands may be executing - any activate or precharge commands have completed prior to changing the frequency - related timing conditions,trcd and trp, have been met prior to changing the frequency - the initial clock frequency must be maintained fo r a minimum of 2 clock cycles after cke goes low - the clock satisfies tch(abs) and tcl(abs) for a mini mum of two clock cycles prior to cke going high. after the input clock frequency is changed and cke is held high, additional mrw commands may be required to set the wr, rl, etc. these settings may need to be adjusted to meet minimum timing requirements at the target clock fre- quency. lpddr2 devices support clock stop during cke low under the following conditions: - ck is held low and ck is held high during clock stop - refresh requirements are met - only refab or refpb commands can be in process - any activate or precharge commands have completed prior to changing the frequency - related timing conditions,trcd and trp, have been met prior to changing the frequency - the initial clock frequency must be maintained fo r a minimum of 2 clock cycles after cke goes low - the clock satisfies tch(abs) and tcl(abs) for a mi nimum of two clock cycles prior to cke going high lpddr2 devices support input clock frequency change during cke high under the following conditions: - tck(abs)min is met for each clock cycle - refresh requirement apply during clock frequency change - any activate, read, write, precharge, mode register write or mode register read comma nds must have executed to completion including any associated data bursts prior to changing the frequency - the related timing conditions (trcd, twr, twra, trp,tmrw,tmrr etc) have been met prior to changing the frequency - cs shall be held high during clock frequency change - during clock frequency change, only refab or refpb commands may be executing - the lpddr2 device is ready for normal operation after the clock satisfies tch(abs) and tcl(abs) for a minimum of 2tck+txp after the input clock frequency is changed and cke is held high, additional mrw commands may be required to set the wr, rl, etc. these settings may need to be adjusted to meet minimum timing requirements at the target clock fre- quency. lpddr2 devices support clock stop during cke high under the following conditions: - ck is held low and ck is held high during clock stop - cs shall be held high during clock stop - refresh requirements are met - only refab or refpb commands can be in process - any activate, read, write, precharge, mode register write or mode register read comma nds must have executed to completion including any associated data bursts prior to stopping the clock - the related timing conditions (trcd, twr, twra, trp, tmrw,tmrr etc) have been met prior to stopping the clock - the lpddr2 device is ready for normal operation after the cl ock is restarted and satisfies tch(abs) and tcl(abs) for a minimum of 2tck+txp AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -73?103- rev.1.0 june 2016 no operation command the purpose of the no operation command (nop) is to pr event the lpddr2 device from registering any unwanted command between operations. only when the cke level is c onstant for clock cycle n-1 and clock cycle n, a nop com- mand may be issued at clock cycle n. a nop command has two possible encodings: 1. cs high at the clock rising edge n. 2. cs low and ca0, ca1, ca2 high at the clock rising edge n. the no operation command will not terminat e a previous operation that is still ex ecuting, such as a burst read or write cycle. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -74 ? 103- rev.1.0 june 2016 absolute maximum dc ratings notes : 1. stresses greater than those listed un der ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of t he device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. see ?power-ramp? for relationships between power supplies. 3. vrefdq =< 0.6 x vddq; however, vrefdq ma y be => vddq provided that vrefdq =< 300mv. 4. vrefca =< 0.6 x vddca; howe ver, vrefca may be => vddca provided that vr efca =< 300mv. 5. storage temperature is the case surface temperature on the center/top side of the lpddr2 device. for the measurement conditions, please refer to jesd51-2 standard. symbol parameter min max units note v dd1 voltage on v dd1 pin relative to vss -0.4 2.3 v 2 v dd2 voltage on v dd2 pin relative to vss -0.4 1.6 v 2 v ddca voltage on v ddca pin relative to vss -0.4 1.6 v 2,4 v ddq voltage on v ddq pin relative to vss -0.4 1.6 v 2,3 vin, vout voltage on any pin relative to vss -0.4 1.6 v tstg storage temperature (plastic) -55 125 c 5 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -75?103- rev.1.0 june 2016 ac/dc operating conditions operating temperature condition notes : 1. operating temperatur e is the case surface temperature on the center/top side of the lpddr2 device. for the mea- surement conditions, please refer to jesd51-2 standard. 2. either the device case temperature rating or the temperature sensor may be used to set an appropriate refresh rate, determine the need for ac timing de-rating and/or monitor the operating temperature. when using the temperature sen- sor, the actual device case temperature may be higher than the toper rating that applies for the standard or extended temperature ranges. fo r example, tcase may be above 85c when the temperature sensor indicates a temperature of less than 85c. recommended dc operating conditions input leakage current notes : 1. the minimum limit requirement is for testing purposes . the leakage current on vrefca and vrefdq pins should be minimal. 2. although dm is for input only, the dm leakage shall match the dq and dqs/dqs output leakage specification. symbol parameter rating units notes t oper operating case temperatur e(commercial) -25 to +85 c t oper operating case temperature(industrial) -40 to +85 c symbol parameter rating units notes min. typ. max. v dd1 core supply voltage 1 1.70 1.80 1.95 v v dd2 core supply voltage 2 1.14 1.20 1.30 v vddca input supply voltage 1.14 1.20 1.30 v v ddq i/o supply voltage 1.14 1.20 1.30 v symbol parameter m in max units notes i l input leakage current for ca, cke, cs , ck, ck any input 0v =< vin =< vddca (all other pins not under test = 0v) -2 2 ua 1 i vref vref supply leakage current vrefdq = vddq/2 or vrefca = vddca/2 (all other pins not under test = 0v) -1 1 ua 2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -76?103- rev.1.0 june 2016 ac and dc input m easurement levels single-ended ac and dc input levels for ca and cs signals notes : 1. for ca and cs input only pins. vref = vrefca(dc). 2. see overshoot and undersh oot specifications section. 3. the ac peak noise on vr efca may not allow vrefca to deviate from vrefca(dc) by more than +/-1% vddca (for reference: ap prox. +/- 12 mv). 4. for reference : approx. vdd/2 12 mv. single-ended ac and dc input levels for cke notes : 1. see overshoot and undersh oot specifications section. single-ended ac and dc input levels for dq and dm signals symbol parameter lpddr2 1600-466 lpddr2 400-200 unit notes min max min max v ihca (ac) ac input logic high vrefca + 0.22v -vrefca + 0.3v -v1,2 v ilca (ac) ac input logic low -vrefca - 0.22v -vrefca + 0.3v v1,2 v ihca (dc) dc input logic high vrefca + 0.13v vddca vrefca + 0.2v vddca v 1 v ilca (dc) dc input logic low vssca vrefca - 0.13v vssca vrefca + 0.2v v1 vrefca(dc) reference voltage for ca and cs inputs 0.49 x vddca 0.51 x vddca 0.49 x vddca 0.51 x vddca v3 , 4 symbol parameter min. max. units notes vihcke cke input high level 0.8 x vddca - v1 vilcke cke input low level - 0.2 x vddca v1 symbol parameter lpddr2 1600-466 lpddr2 400-200 unit notes min max min max v ihdq (ac) ac input logic high vrefca + 0.22v -vrefca + 0.3v -v1,2 v ildq (ac) ac input logic low -vrefca - 0.22v -vrefca + 0.3v v1,2 v ihdq (dc) dc input logic high vrefca + 0.13v vddq vrefca + 0.2v vddq v 1 v ildq (dc) dc input logic low vssq vrefca - 0.13v vssq vrefca + 0.2v v1 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -77?103- rev.1.0 june 2016 notes : 1. for dq input only pins. vref = vrefdq(dc). 2. see overshoot and undersh oot specifications section. 3. the ac peak noise on vrefdq may not allow vrefdq to deviate from vrefdq(dc) by more than +/-1% vdddq (for reference: ap prox. +/- 12 mv). 4. for reference : approx. vdd/2 12 mv. vrefdq(dc) reference voltage for dq and dm inputs 0.49 x vddq 0.51 x vddq 0.49 x vddq 0.51 x vddq v3,4 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -78?103- rev.1.0 june 2016 vref tolerances the dc tolerance limits and ac noise limits for the refer ence voltages vrefca and vrefdq are illustrated bellow. this figure shows a valid reference voltage vref(t) as a func tion of time. vdd is used in place of vddca for vrefca, and vddq for vrefdq. vref(dc) is the linear average of vref (t) over a very long period of time (e.g., 1 second) and is specified as a fraction of the linear average of vddq or vddca, also over a very long period of time (e.g., 1 second). this average must meet the min/max re quirements. additionally, vref(t) can te mporarily deviate from vref(dc) by no more than +/-1% vdd. vref(t) cannot track noise on vddq or vddca if doing so would force vref outside these specifications. the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac), and vil(dc) are dependent on vref. vref dc variations affect the absolute voltage a signal must reach to achieve a valid high or low, as well as the time from which setup and hold times are measured. when vref is outside the specified levels, devices will func- tion correctly with appropriate timing deratings as long as: vref is maintained between 0.44 x vddq (or vddca) and 0. 56 x vddq (or vddca), and t he controller achieves the required single-ended ac and dc input levels from instantaneous vref. system timing and voltage budgets must account for vref deviations outside this range. this also clarifies that the lpddr2 setup/hold specification and derating values need to include time and voltage asso- ciated with vref ac-noise. timing and voltage effects due to ac-noise on vref up to the specified limit (+/- 1% of vdd) are included in lpddr2 timings and their associated deratings. vref(dc) toler a nce a nd vref ac-noise li m its volta g e v dd v ss tim e AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -79?103- rev.1.0 june 2016 input signals lpddr2-466 to lpddr2-1066 input signal notes: 1. numbers reflect typical values. 2. for ca[9:0], ck, ck , cs , and cke, vdd stands for vddca. for dq, dm, dqs, and dqs , vdd stands for vddq. 3. for ca[9:0], ck, ck , cs , and cke, vss stands for vssca. for dq, dm, dqs, and dqs , vss stands for vssq. v ih( a c) v ih(dc) 0.8 2 0v 0.730 v 0. 62 4v 0. 61 2v 0. 600 v 0.588 v 0.57 6v 0.470 v 0.380 v v il(dc) v il( a c) 0.82 0 v 0.730v 0.624 v 0.6 1 2v 0.6 00v 0.588v 0.576v 0.470v 0.380v minimum vil and vih levels 1.2 00v 0.000v -0.350v vil and vih levels with ringback 1.550v v dd + 0.35 v v dd v ih( a c) v ih(dc) v ref + a c noise v ref + dc error v ref - dc error v ref - a c noise v il(dc) v il( a c) vss vss - 0.35 v AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -80?103- rev.1.0 june 2016 lpddr2-200 to lpddr2-400 input signal notes: 1. numbers reflect typical values. 2. for ca[9:0], ck, ck , cs , and cke, vdd stands for vddca. for dq, dm, dqs, and dqs , vdd stands for vddq. 3. for ca[9:0], ck, ck , cs , and cke, vss stands for vssca. for dq, dm, dqs, and dqs , vss stands for vssq. v ih( a c) v ih(dc) 0.900 v 0.800 v 0. 62 4v 0. 61 2v 0. 600 v 0.588 v 0.57 6v 0.400 v 0.300 v v il(dc) v il( a c) 0.900v 0.800v 0.624 v 0.6 1 2v 0.6 00v 0.588v 0.576v 0.400v 0.300v minimum vil and vih levels 1.2 00v 0.000v -0.350v vil and vih levels with ringback 1.550v v dd + 0.35 v v dd v ih( a c) v ih(dc) v ref + a c noise v ref + dc error v ref - dc error v ref - a c noise v il(dc) v il( a c) vss vss - 0.35 v AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -81?103- rev.1.0 june 2016 ac and dc logic input levels for differential signals differential signals definition differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) differential ac and dc input levels notes : 1. used to define a differential signal slew-rate. for ck - ck use vih/vil(dc) of addre ss/command and vrefca; for strobes (dqs, dqs ) use vih/vil(dc) of dqs and vrefdq; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here. symbol parameter lpddr2 1600-466 lpddr2 400-200 unit notes min max min max v ihdiff (ac) differential input high 2 x (vih(ac) - vref) note 3 2 x (vih(ac) - vref) note 3 v 2 v ildiff (ac) differential input low note 3 2 x (vil(ac) - vref) note 3 2 x (vil(ac) - vref) v2 v ihdiff (dc) differential input high 2 x (vih(dc) - vref) note 3 2 x (vih(dc) - vref) note 3 v 1 v ildiff (dc) differential input low note 3 2 x (vil(dc) - vref) note 3 2 x (vil(dc) - vref) v1 definition of differenti al ac -swing a nd "tim e abo ve ac le v el" tdvac 0.0 tdvac v ih .diff.min hal f cycle sqd-sqd .e.i( e g atlov tupni laitnere ff id kc-kc , ) ti m e tdvac v ih .diff.ac.min v il .diff.ma x v il .diff.ac.ma x AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -82?103- rev.1.0 june 2016 2. for ck - ck use vih/vil(ac) of ca and vrefca; for dqs - dqs , use vih/vil(ac) of dqs and vrefdq; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, howe ver the single-ended signals ck, ck , dqs, and dqs must be within the respec- tive limits (vih(dc)max, vil(dc)min) for single-ended signals and must comply with the specified limitations for over- shoot and undershoot. allowed time before ringback (tdvac) for ck - ck and dqs - dqs slew rate [v/ns] tdvac [ps] @ |vih/ ldiff(ac)| = 440mv tdvac [ps] @ |vih/ ldiff(ac)| = 600mv min. min. > 4.0 175 75 4.0 170 57 3.0 167 50 2.0 163 38 1.8 162 34 1.6 161 29 1.4 159 22 1.2 155 13 1.0 150 0 < 1.0 150 0 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -83?103- rev.1.0 june 2016 single-ended requirements for differential signals each individual component of a differential signal (ck, dqs, ck , dqs ) has also to comply with certain requirements for single-ended signals. ck and ck shall meet vseh(ac) min / vs el(ac) max in every half-cycle. dqs, dqs shall meet vseh(ac) min / vsel(ac) max in every half-cycle proceeding and following a valid transition. note that the applicable ac-levels for ca and dq?s are different per speed-bin. note that while ca and dq signal requirements are with respect to vref, the single-ended components of differential signals have a requirement with respect to vddq/2 for dqs, dqs and vddca/2 for ck, ck ; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. for single-ended compo- nents of differential signals the requirement to reach vsel(ac) max, vseh(ac) min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. sing le-ended re q uirement for diff erential signals vss or vssq vdd or vddq vsel m ax vseh m in vseh vsel tim e vdd/2 or vddq/2 ck or dqs AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -84?103- rev.1.0 june 2016 single-ended levels for ck, dqs, ck , dqs notes : 1. for ck, ck use vih/vil(ac) of ca; for strobes (dqs, dqs ) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vseh(ac) /vsel(ac) for ca is based on vrefca; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however the sing le-ended components of differential signals ck, ck , dqs, dqs need to be within the respective limits (vih (dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. refer to "overshoot and undershoot specifications?. differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differenti al input signals (ck, ck and dqs, dqs ) must meet the requirements in below table. the differ- ential input cross point voltage vix is measured from the act ual cross point of true and complement signal to the mid level between of vdd and vss. symbol parameter lpddr21600-466 lpddr400-200 unit notes min max min max vseh(ac) single-ended high-level for strobes (vddq/2) + 0.22 note 3 (vddq/2) + 0.3 note 3 v2 single-ended high-level for ck, ck (vddca/2) + 0.22 note 3 (vddca/2) + 0.3 note 3 v2 vsel(ac) single-ended low-level for strobes note 3 (vddq/2) - 0.22 note 3 (vddq/2) - 0.22 v1 single-ended low-level for ck, ck note 3 (vddca/2) - 0.22 note 3 (vddca/2) - 0.22 v1 vi x definition v dd ck , dqs v dd /2 ck, dqs v ss v i x v i x v i x AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -85?103- rev.1.0 june 2016 cross point voltage for differential input signals ( ck, dqs ) notes : 1. the typical value of vix(ac) is expect ed to be about 0.5 x vdd of the transmitti ng device, and vix(ac) is expected to track variations in vdd. vix(ac) indicates the volt age at which differential input sig-nals must cross. 2. for ck and ck , vref = vrefca(dc). for dqs and dqs , vref = vrefdq(dc). differential input sl ew rate definition notes : the differential signal (i.e. ck - ck and dqs - dqs ) must be linear between these thresholds. symbol parameter min. max. units notes vixca differential input cross point voltage relative to vddca/2 for ck, ck -120 120 mv 1,2 vixdq differential input cross point volt age relative to vdddq/2 for dqs, dqs -120 120 mv 1,2 description measured defined by from to differential input slew rate for rising edge ( ck-ck and dqs-dqs ) vildiff (max) vihdiff (min) vihdiff (min) - vildiff (max) delta trdiff differential input slew rate for falling edge ( ck-ck and dqs-dqs ) vihdiff (min) vildiff (max) vihdiff (min) - vildiff (max) delta tfdiff differentia l input slew r a te definition for dqs, dqs , a nd ck, ck v ihdi ffm in 0 v ildi ffm ax delta trdi ff delta tfdi ff AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -86 ? 103- rev.1.0 june 2016 ac and dc outp ut measurement levels single-ended ac & dc output levels notes : 1. ioh = -0.1ma. 2. iol = -0.1ma. differential ac & dc output levels notes : 1. ioh = -0.1ma. 2. iol = -0.1ma. single-ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ended signals. notes : output slew rate is verified by design and char acterization, and may not be subject to production test. symbol parameter lpddr2-1600 to lpddr2-200 units notes voh(dc) dc output high measurement level (for iv curve linearity) 0.9 x vddq v 1 vol(dc) dc output mid measurement level (for iv curve linearity) 0.1 x vddq v 2 voh(ac) ac output high measurement level (for output sr) vrefdq+0.12 v vol(ac) ac output low measurement level (for output sr) vrefdq-0.12 v i oz output leakage current (dq, dm, dqs, dqs) (dq, dqs, dqs are disabled; 0v =< vout =< vddq) -5 (min) ua 5 (max) ua mm pupd delta ron between pull-up and pull-down for dq/dm -15 (min) % 15 (max) % symbol parameter lpddr2-1600 to lpddr2-200 units notes vohdiff(ac) ac differential output high measurement level (for output sr) +0.2 x vddq v voldiff(ac) ac differential output low measurement level (for output sr) -0.2 x vddq v description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) delta trse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) delta trse AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -87 ? 103- rev.1.0 june 2016 description : sr : slew rate q : query output (like in dq, which stands for data-in, query-output) se : single-ended signals notes : 1. measured with output reference load. 2. the ratio of pull-up to pull-down slew rate is specified for the same temper ature and voltage, over the entire tempera- ture and voltage range. for a given output, it represents th e maximum difference between pull-up and pull-down drivers due to process variation. 3. the output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac). 4. slew rates are measured under normal sso conditions, with 1/2 of dq signals pe r data byte driving logic-high and 1/ 2 of dq signals per data byte driving logic-low. parameter symbol lpddr2-1600 to lpddr2-200 units min max single ended output slew rate (ron = 40 +/- 30%) srqse 1.5 3.5 v/ns single ended output slew rate (ron = 60 +/- 30%) srqse 1 2.5 v/ns output slew-rate matching ratio (pull-up to pull-down) 0.7 1.4 single-ended output slew r a te definition AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -88?103- rev.1.0 june 2016 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between voldiff(ac) and voh-diff(ac) for differential signals. notes : output slew rate is verified by design and char acterization, and may not be subject to production test. description : sr : slew rate q : query output (like in dq, which stands for data-in, query-output) diff : differential signals notes : 1. measured with output reference load. 2. he output slew rate for falling and rising edges is defined and measured bet ween vol(ac) and voh(ac). 3. slew rates are measured under normal sso conditions, with 1/2 of dq signals pe r data byte driving logic-high and 1/ 2 of dq signals per data byte driving logic-low. description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) v ohdiff(ac)-voldiff(ac) delta trdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) v ohdiff(ac)-voldiff(ac)) delta tfdiff parameter symbol lpddr2-1600 to lpddr2-200 units min max single ended output slew rate (ron = 40 +/- 30%) srqdiff 3.0 7.0 v/ns single ended output slew rate (ron = 60 +/- 30%) srqdiff 2.0 5.0 v/ns differentia l output slew r a te definition AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -89?103- rev.1.0 june 2016 overshoot and unde rshoot specification ac overshoot/undersho ot specifications notes: 1. for ca0-9, ck, ck , cs , and cke, vdd stands for vddca. for dq, dm, dqs, and dqs , vdd stands for vddq. 2. for ca0-9, ck, ck , cs , and cke, vss stands for vssca. for dq, dm, dqs, and dqs , vss stands for vssq. 3. maximum peak amplitude values are re ferenced from actual vdd and vss values. 4. maximum area values are referenced from maximum operating vdd and vss values. parameter specification unit 1066 933 800 667 533 466 400 333 266 200 maximum peak amplitude allowed for overshoot area 0.35 v maximum peak amplitude allowed for undershoot area 0.35 v maximum overshoot area above vdd 0.15 0.17 0.20 0.24 0.30 0.35 0.40 0.48 0.60 0.80 v-ns maximum undershoot area below vss 0.15 0.17 0.20 0.24 0.30 0.35 0.40 0.48 0.60 0.80 v-ns address and control overshoot and undershoot definition AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -90?103- rev.1.0 june 2016 input/output capacitance notes : 1. this parameter applies to die device only (does not include package capacitance). 2. 2this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147 (procedure for measuring input capacitance using a vector network analyzer) with vdd1, vdd2, vddq, vss, vssca, vssq a pplied and all othe r pins floating. 3. absolute value of cck-cck 4. ci applies to cs , cke, ca0-ca9. 5. cdi = ci - 0.5 * (cck + cck) 6. dm loading matches dq and dqs. 7. mr3 i/o configuration ds op3- op0 = 0001b (34.3 ohm typical). 8. absolute value of cdqs and cdqs . 9. cdio = cio - 0.5 * (cdqs + cdqs ) in byte-lane. 10. maximum external load capacitance on zq pin, incl uding packaging, board, pin, resistor, and other lpddr2 devices: 5 pf. parameter symbol lpddr2 1066-466 lpddr2 400-200 units note min max min max input capacitance (ck and ck ) cck 1 2 1 2 pf 1,2 input capacitance delta (ck and ck ) cdck 0 0.2 0 0.25 pf 1,2,3 input capacitance (all other input-only pins) ci 1 2 1 2 pf 1,2,4 input capacitance delta (all other input-only pins) cdi -0.4 0.4 -0.5 0.5 pf 1,2,5 input/output capacitance (dq, dqs, dqs , dm) cio 1.25 2.5 1.25 2.5 pf 1,2,6,7 input/output capacitance delta (dqs and dqs ) cddqs 0 0.25 0 0.3 pf 1,2,7,8 input/output capacitance delta (dq, dm) cdio -0.5 0.5 -0.6 0.6 pf 1,2,7,9 input/output capacitance: zq czq 0 2.5 0 2.5 pf 1,2 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -91?103- rev.1.0 june 2016 idd specification (vdd2, vddq,vddca = 1.14~1.30v, vdd1 = 1.70~1.95v) conditions symbol power supply 1066 unit operating one bank active-precharge current: tck = tck(avg)min; trc = trcmin; cke is high; cs is high between valid commands; ca bus inputs are switching; data bus inputs are stable idd0 1 idd0 2 idd0 in vdd1 vdd2 vddca,vddq 15 70 10 ma idle power-down standby current: tck = tck(avg)min; cke is low; cs is high; all banks/rbs idle; ca bus inputs are switching; data bus inputs are stable idd2p 1 idd2p 2 idd2p in vdd1 vdd2 vddca,vddq 600 800 120 ua idle power-down standby current with clock stop: ck =low, ck =high; cke is low; cs is high; all banks/rbs idle; ca bus inputs are stable; data bus inputs are stable idd2ps 1 idd2ps 2 idd2ps in vdd1 vdd2 vddca,vddq 600 800 120 ua idle non power-down standby current: tck = tck(avg)min; cke is high; cs is high; all banks/rbs idle; ca bus inputs are switching; data bus inputs are stable idd2n 1 idd2n 2 idd2n in vdd1 vdd2 vddca,vddq 2 20 10 ma idle non power-down standby current with clock stop: ck_t =low, ck_c =high; cke is high; cs is high; all banks/rbs idle; ca bus inputs are stable; data bus inputs are stable idd2ns 1 idd2ns 2 idd2ns in vdd1 vdd2 vddca,vddq 1.7 10 6 ma active power-down standby current: tck = tck(avg)min; cke is low; cs is high; one bank/rb active; ca bus inputs are switching; data bus inputs are stable idd3p 1 idd3p 2 idd3p in vdd1 vdd2 vddca,vddq 1000 7.5 150 ua ma ua AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -92?103- rev.1.0 june 2016 active power-down standby current with clock stop: ck=low, ck =high; cke is low; cs is high; one bank/rb active; ca bus inputs are stable; data bus inputs are stable idd3ps 1 idd3ps 2 idd3ps in vdd1 vdd2 vddca,vddq 1200 7.5 150 ua ma ua active non power-down standby current: tck = tck(avg)min; cke is high; cs is high; one bank/rb active; ca bus inputs are switching; data bus inputs are stable idd3n 1 idd3n 2 idd3n in vdd1 vdd2 vddca,vddq 2 25 10 ma active non power-down standby current with clock stop: ck=low, ck =high; cke is high; cs is high; one bank/rb active; ca bus inputs are stable; data bus inputs are stable idd3ns 1 idd3ns 2 idd3ns in vdd1 vdd2 vddca,vddq 2 20 6 ma operating burst read current: tck = tck(avg)min; cs is high between valid commands; one bank/rb active; bl = 4; rl = rlmin; ca bus inputs are switching; 50% data change each burst transfer idd4r 1 idd4r 2 idd4r in idd4r q vdd1 vdd2 vddca vddq 3 250 10 ma operating burst write current: tck = tck(avg)min; cs is high between valid commands; one bank/rb active; bl = 4; wl = wlmin; ca bus inputs are switching; 50% data change each burst transfer idd4w 1 idd4w 2 idd4w in vdd1 vdd2 vddca,vddq 3 250 35 ma all bank refresh burst current: tck = tck(avg)min; cke is high between valid commands; trc = trfcabmin; burst refresh; ca bus inputs are switching; data bus inputs are stable idd5 1 idd5 2 idd5 in vdd1 vdd2 vddca,vddq 20 150 10 ma all bank refresh average current: tck = tck(avg)min; cke is high between valid commands; trc = trefi; ca bus inputs are switching; data bus inputs are stable idd5ab 1 idd5ab 2 idd5ab in vdd1 vdd2 vddca,vddq 5 25 10 ma conditions symbol power supply 1066 unit AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -93?103- rev.1.0 june 2016 notes : 1. published idd values are the maximum of the distribution of the arithmetic mean. 2. idd current specific ations are tested after the devi ce is properly initialized. 3. the 1x self refresh rate is the rate at which the device is refreshed internally during self refresh, before going into the extended temper ature range. 4. measured currents are the su mmation of vddq and vddca. 5. guaranteed by desi gn with output load of 5pf and ron = 40ohm. 6. per bank refresh only applicable for lpdd r2-s4 devices of 1gb or higher densities 7. this is the general definition that applies to full-array self refresh). 8. idd6et is typical values idd6 partial array self-refresh current per bank refresh average current: tck = tck(avg)min; cke is high between valid commands; trc = trefi/8; ca bus inputs are switching; data bus inputs are stable idd5pb 1 idd5pb 2 idd5pb in vdd1 vdd2 vddca,vddq 5 25 10 ma self refresh current (standard temperature range): ck=low, ck =high; cke is low; ca bus inputs are stable; data bus inputs are stable; maximum 1x self-refresh rate idd6 1 idd6 2 idd6 in vdd1 vdd2 vddca,vddq 1000 4000 120 ua self refresh current (+85?c to +105?c): ck=low, ck =high; cke is low; ca bus inputs are stable; data bus inputs are stable; idd6et 1 idd6et 2 idd6et in vdd1 vdd2 vddca,vddq tbd tbd tbd ma pasr supply 1066 unit full array vdd1 vdd2 vddca,vddq 1000 4000 120 ua 1/2 array vdd1 vdd2 vddca,vddq 950 2300 120 ua 1/4 array vdd1 vdd2 vddca,vddq 900 1500 120 ua 1/8 array vdd1 vdd2 vddca,vddq 850 1060 120 ua conditions symbol power supply 1066 unit AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -94?103- rev.1.0 june 2016 refresh requirements by device density lpddr2-s4 refresh requirement parameters (per density) symbol parameter 4gb(single die) 8gb(dual dies) unit number of banks 8 trefw refresh window: tcase =< 85?c 32 ms trefw refresh window: 85?c < tcase =< 105?c 8 ms r required number of refresh commands (min) 8192 8192 trefi average time between refresh commands (for reference only) tcase <= 85?c 3.9 3.9 us trefipb 0.4875 0.4875 us trfcab refresh cycle time 130 130 ns trfcpb per-bank refresh cycle time 60 60 ns trefbw burst refresh window = 4 x 8 x trfcab 4.16 4.16 us AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -95 ? 103- rev.1.0 june 2016 ac characteristics (vdd2, vddq,vddca = 1.14~1.30v, vdd1 = 1.70~1.95v) parameter symbol min/max min tck speed grade unit 1066 800 clock timing max. frequency ~ 533 400 mhz average clock period tck(avg) min 1.875 2.5 ns max 100 average high pulse width tch(avg) min 0.45 tck(avg) max 0.55 average low pulse width tcl(avg) min 0.45 tck(avg) max 0.55 absolute clock period tck(abs) min tck(avg)min + tjit(per),min ps absolute clock high pulse width (with allowed jitter) tch(abs), allowed min 0.43 tck(avg) max 0.57 absolute clock low pulse width (with allowed jitter) tcl(abs), allowed min 0.43 tck(avg) max 0.57 clock period jitter (with allowed jitter) tjit(per), allowed min -90 -100 ps max 90 100 maximum clock jitter between two consecutive clock cycles (with allowed jitter) tjit(cc), allowed max 180 200 ps duty cycle jitter (with allowed jitter) tjit(duty), allowed min min((tch(abs),min - tch(avg),min), (tcl(abs),min - tcl(avg),min)) * tck(avg) ps max max((tch(abs),max - tch(avg),max), (tcl(abs),max - tcl(avg),max)) * tck(avg) cumulative error across 2 cycles terr(2per), allowed min -132 -147 ps max 132 147 cumulative error across 3 cycles terr(3per), allowed min -157 -175 ps max 157 175 cumulative error across 4 cycles terr(4per), allowed min -175 -194 ps max 175 194 cumulative error across 5 cycles terr(5per), allowed min -188 -209 ps max 188 209 cumulative error across 6 cycles terr(6per), allowed min -200 -222 ps max 200 222 cumulative error across 7 cycles terr(7per), allowed min -209 -232 ps max 209 232 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -96?103- rev.1.0 june 2016 cumulative error across 8 cycles terr(8per), allowed min -217 -241 ps max 217 241 cumulative error across 9 cycles terr(9per), allowed min -224 -249 ps max 224 249 cumulative error across 10 cycles terr(10per), allowed min -231 -257 ps max 231 257 cumulative error across 11 cycles terr(11per), allowed min -237 -263 ps max 237 263 cumulative error across 12 cycles terr(12per), allowed min -242 -269 ps max 242 269 cumulative error across n = 13, 14 . . . 49, 50cycles terr(nper), allowed min terr(nper),allowed,min = (1 + 0.68ln(n)) * tjit(per),allowed,min ps max terr(nper),allowed,max = (1 + 0.68ln(n)) * tjit(per),allowed,max zq calibration parameters initialization calibration time tzqinit min 1 us long calibration time tzqcl min 6 360 ns short calibration time tzqcs min 6 90 ns calibration reset time tzqreset min 3 50 ns read parameters dqs output access time from ck/ck tdqsck min 2500 ps max 5500 dqsck delta short tdqsckds max 330 450 ps dqsck delta medium tdqsckdm max 680 900 ps dqsck delta long tdqsckdl max 920 1200 ps dqs - dq skew tdqsq max 200 240 ps data hold skew factor tqhs max 230 280 ps dqs output high pulse width tq sh min tch(abs) - 0.05 tck(avg) dqs output low pulse width tqsl min tcl(abs) - 0.05 tck(avg) data half period tqhp min min(tqsh, tqsl) tck(avg) dq / dqs output hold time from dqs tqh min tqhp - tqhs ps read preamble trpre min 0.9 tck(avg) read postamble trpst min tcl(abs) - 0.05 tck(avg) dqs low-z from clock tlz(dqs) min tdqsck(min) - 300 ps dq low-z from clock tlz(dq) min tdqsck(min) - (1.4 * tqhs(max)) ps parameter symbol min/max min tck speed grade unit 1066 800 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -97?103- rev.1.0 june 2016 dqs high-z from clock thz(dqs) max tdqsck(max) - 100 ps dq high-z from clock thz(dq) max tdq sck(max) + (1.4 * tdqsq(max)) ps write parameters dq and dm input hold time (vref based) tdh min 210 270 ps dq and dm input setup time (vref based) tds min 210 270 ps dq and dm input pulse width tdipw min 0.35 tck(avg) write command to 1st dqs latching transition tdqss min 0.75 tck(avg) max 1.25 dqs input high-level width tdqsh min 0.4 tck(avg) dqs input low-level width tdqsl min 0.4 tck(avg) dqs falling edge to ck setup time tdss min 0.2 tck(avg) dqs falling edge hold time from ck tdsh min 0.2 tck(avg) write postamble twpst min 0.4 tck(avg) write preamble twpre min 0.35 tck(avg) cke input parameters cke min. pulse width (high and low pulse width) tcke min 3 3 tck(avg) cke input setup time tiscke min 0.25 tck(avg) cke input hold time tihcke min 0.25 tck(avg) command address input parameters address and control input setup time (vref based) tis min 220 290 ps address and control input hold time (vref based) tih min 220 290 ps address and control input pulse width tipw min 0.4 tck(avg) mode register parameters mode register write command period tmrw min 5 5 tck(avg) mode register read command period tmrr min 2 2 tck(avg) lpddr2 sdram core parameters read latency rl min 3 8 6 tck(avg) write latency wl min 1 4 3 tck(avg) active to active command period trc min tras + trpab (with all-bank precharge) tras + trppb (with per-bank precharge) ns cke min. pulse width during self-refresh (low pulse width during self-refresh) tckesr min 3 15 ns self refresh exit to next valid command delay txsr min 2 trfcab + 10 ns parameter symbol min/max min tck speed grade unit 1066 800 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -98?103- rev.1.0 june 2016 exit power down to next valid command delay txp min 2 7.5 ns cas to cas delay tccd min 2 2 tck(avg) internal read to precharge command delay trtp min 2 7.5 ns ras to cas delay trcd min 3 18 ns row precharge time(single bank) trppb min 3 18 ns row precharge time(all banks) trpab 8-bank min 3 21 ns row active time tras min 3 42 ns max - 70 us write recovery time twr min 3 15 ns internal write to read command delay twtr min 2 7.5 ns active bank a to active bank b trrd min 2 10 ns four bank activate window tfaw min 8 50 ns minimum deep power down time tdpd min 500 us lpddr2 temperature de-rating tdqsck de-rating tdqsck (derated) max 5620 6000 ps core timings temperature de-rating trcd (derated) min trcd + 1.875 ns trc (derated) min trc + 1.875 ns tras (derated) min tras + 1.875 ns trp (derated) min trp + 1.875 ns trrd (derated) min trrd + 1.875 ns boot parameters (10 mhz - 55 mhz) clock cycle time tckb min 18 ns max 100 cke input setup time tisckeb min 2.5 ns cke input hold time tihckeb min 2.5 ns address & control input setup time tisb min 1150 ps address & control input hold time tihb min 1150 ps dqs output data access time from ck/ck tdqsckb min 2 ns max 10 dqs - dq skew tdqsqb max 1.2 ns parameter symbol min/max min tck speed grade unit 1066 800 AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -99?103- rev.1.0 june 2016 notes for ac electrical characteristics 1. frequency values are for reference only. clock cycle ti me (tck) is used to determi ne device capabilities. 2. all ac timings assume an input slew rate of 1 v/ns. 3. read, write, and input setup and hold values are referenced to vref. 4. tdqsckds is the absolute value of the difference betw een any two tdqsck measurements (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window. td qsckds is not tested and is guaranteed by design. tem- perature drift in the system is < 10 ?c/s. values do not include clock jitter. . 5. tdqsckdm is the absolute value of the difference betw een any two tdqsck measurements (in a byte lane) within a 1.6us rolling window. tdqsckdm is not test ed and is guaranteed by design. temperature drift in the system is < 10 ?c/s. values do not include clock jitter. 6. tdqsckdl is the absolute value of the difference between any two tdqsck measurements (in a byte lane) within a 32ms rolling window. tdqsckdl is not tested and is guarantee d by design. temperature drift in the system is < 10 ?c/ s. values do not include clock jitter. 7. for low-to-high and high-to-low transitions, the timing reference is at the point when the signal crosses the transition threshold (vtt). thz and tlz transitions occur in the same access time (with resp ect to clock) as valid data transitions. these parameters are not refe renced to a specific voltage level but to the time when the device output is no longer driving (for trpst, thz(dqs) an d thz(dq)), or begins driving (for trpr e, tlz(dqs), tlz(dq)). figure shows a method to calculate the point when device is no longer driv ing thz (dqs) and thz (dq), or begins driving tlz (dqs), tlz (dq) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. hsul_12 driver output reference load for timing and skew rate the parameters tlz(dqs), tlz(dq), thz(dqs), and thz(dq ) are defined as single-ended. the timing parameters trpre and trpst are determined from the differential signal dqs-dqs . 8. measured from the point when dqs, dqs begins driving the signal to the point when dqs, dqs begins driving the first rising strobe edge. 9. measured from the last fa lling strobe edge of dqs, dqs to the point when dqs, dqs finishes driving the signal. 10. cke input setup time is measured from c ke reaching a high/low voltage level to ck, ck crossing. 11. cke input hold time is measured from ck, ck crossing to cke reaching a high/low voltage level. 12. input set-up/hold time for signal (ca[9:0], cs ). 13. to ensure device operation before the device is confi gured, a number of ac boot-timing parameters are defined in this table. boot parameter symbols have the letter b appended (for example, tck during boot is tckb). data hold skew factor tqhsb max 1.2 ns parameter symbol min/max min tck speed grade unit 1066 800 thz(dqs ), thz(d q ) stop driving point = 2 x t1 - t 2 v ol + 2 x x m v t1 t 2 v ol + x m v v oh - x mv v oh - 2 x x mv tlz(dqs ), tlz(d q ) begin driving point = 2 x t1 - t 2 v ol v tt - y m v v oh t 2 t1 v tt - 2 x y m v v tt + 2 x y m v v tt + y mv v tt v tt y 2 x y actual waveform x 2 x x AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -100?103- rev.1.0 june 2016 14. the lpddr device will set some mode register default va lues upon receiving a reset command as specified in mode register definition. 15. the output skew parameters are measured with defa ult output impedance settings using the reference load. 16. the minimum tck column applies only when tck is greater than 6ns. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -101?103- rev.1.0 june 2016 package diagram 134-ball fbga - 11.5mm x 11.5mm 0.65mm pitch unit: mm * bsc (basic spacing between center) AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -102?103- rev.1.0 june 2016 part numbering system as4c 128 m32md2 18 b c / i n dram 128 m 32 = 128 mx32 m d 2 = lpddr2 18=533 mhz b = fbga c=commercial (-25 c~+85 c) i = industrial (-40 c~+85 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650-6 10-6800 fax: 650-620-9211 www.alliancememory.com copyright ?alliance memory all rights reserved ?copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in l ife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. AS4C128M32MD2-18BCN as4c128m32md2-18bin confidential -103?103- rev.1.0 june 2016 |
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